Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories

Haron, Nor Zaidi; Hamdioui, Said

doi:10.1109/dft.2009.37

Cited by 8 publications

(4 citation statements)

References 14 publications

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“…Memristors are non-linear two terminal devices that can memorize the resistive state. The combination of novel devices and advanced circuit architecture enables RRAM to offer benefits such as ultrascale storage capacity, low power consumption and fast data access [1][2][3].…”

Section: 10 Introductionmentioning

confidence: 99%

“…Although potentially to be the main future memory, there are many challenges need to be addressed including design, fabrication, performance-cost, quality and reliability issues [2]. In terms of quality and reliability, RRAM is anticipated to be impacted by high manufacturing defects and faults [3][4][5]. Testing for quality and reliability improvement requires engineers to study the behavior of the product they manufactured.…”

Section: 10 Introductionmentioning

confidence: 99%

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Performance Analysis of Memristor Models for RRAM Cell Array Design using SILVACO EDA

2014

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Resistive Random Access Memory (RRAM) is gaining attention as one of the prominent contenders to replace the conventional memory technologies such as SRAM, DRAM and Flash. This emerging memory uses scaled CMOS devices (22 nm or less) to form the peripheral circuits such as decoder and sense amplifier; while a non-CMOS device known as memristor is used to form the cell array. Although potentially becoming the main future memory, RRAM is anticipated to be impacted by the high manufacturing defect density that in turn might lead to quality and reliability problems. This paper presents the initial work towards producing a high quality and reliable RRAM devices. A design and simulation of three memristor SPICE models published in prominent literatures were performed using Silvaco EDA simulation tool. The aim is to identify the optimal model to be used in our RRAM design, which is based on 22 nm CMOS technology. Performance analysis shows that the model proposed by D. Biolek is suitable to be used in our RRAM design.

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Section: 10 Introductionmentioning

confidence: 99%

Section: 10 Introductionmentioning

confidence: 99%

Performance Analysis of Memristor Models for RRAM Cell Array Design using SILVACO EDA

2014

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“…According to [5], [6], defects and faults in crossbar memories tend to induce cluster errors; hence, ECCs able to correct such errors, such as RS [12] and RRNS [13]- [15], are required. Traditionally, these ECCs have been implemented using software resulting in low performance; this make such implementation unsuitable for scalable yet unreliable crossbar memories.…”

Section: Introductionmentioning

confidence: 99%

ECC design for fault-tolerant crossbar memories: A case study

Haron

Hamdioui

Ahyadi

2010

2010 5th International Design and Test Workshop

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Abstract-Crossbar memories are promising memory technologies for future data storage. Although the memories offer trillion-capacity of data storage at low cost, they are expected to suffer from high defect densities and fault rates impacting their reliability. Error correction codes (ECCs), e.g., Redundant Residue Number System (RRNS) and Reed Solomon (RS) have been proposed to improve the reliability of memory systems. Yet, the implementation of the ECCs was usually done at software level, which incurs high cost. This paper analyzes ECC design for fault-tolerant crossbar memories. Both RS and RRNS codes are implemented and experimentally compared in terms of their area overhead, speed and error correction capability. The results show that the encoder and decoder of RS requires 7.5× smaller area overhead and operates 8.4× faster as compared to RRNS. Both ECCs has fairly similar error correction capability.

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“…RRNS encoders and decoders can be added into a hybrid memory with respect to each modulo channel. In [55], two modified RRNS based error correcting codes were proposed for hybrid memories: (1) Three Non- Injected channel faults can be corrected before final outputs are retrieved.…”

Section: Future Workmentioning

confidence: 99%

An FPGA implementation of redundant residue number system for low-cost fast speed fault-tolerant computations

Zhang¹

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Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories

Cited by 8 publications

References 14 publications

Performance Analysis of Memristor Models for RRAM Cell Array Design using SILVACO EDA

Performance Analysis of Memristor Models for RRAM Cell Array Design using SILVACO EDA

ECC design for fault-tolerant crossbar memories: A case study

An FPGA implementation of redundant residue number system for low-cost fast speed fault-tolerant computations

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