Using parallelization and hardware concurrency to improve the performance of a genetic algorithm

Abstract

SUMMARYGenetic algorithms (GAs) are powerful tools for solving many problems requiring the search of a solution space having both local and global optima. The main drawback for GAs is the long execution time normally required for convergence to a solution. This paper discusses three different techniques that can be applied to GAs to improve overall execution time. A serial software implementation of a GA designed to solve a task scheduling problem is used as the basis for this research. The execution time of this implementation is then improved by exploiting the natural parallelism present in the algorithm using a multiprocessor. Additional performance improvements are provided by implementing the original serial software GA in dedicated reconfigurable hardware using a pipelined architecture. Finally, an advanced hardware implementation is presented in which both pipelining and duplicated hardware modules are used to provide additional concurrency leading to further performance improvements.

Applying electromagnetism-like mechanism for feature selection

“…Conducting exhaustive research is time consuming because there are 2 n À 1 possible subsets of features in n-dimensional space. Although this study utilized the metaheuristics to replace brute force search methods, long execution time is usually required to determine a solution [46]. Furthermore, conventional kNN classification is laborious and time-consuming in manually labeled subjects [49]; thus, the proposed method in this study was compared only with GA + 1NN in relation to executing time.…”

“…The CPU time of the proposed method was compared with that of other algorithms. Among the methods compared, only EM and GA belonged to metaheuristics, which normally require long execution time for convergence of a solution [46]. Additionally, conventional kNN classification methods are time-consuming for manually labeled subjects [49].…”

Parallel Implementation of K-Means Algorithm on FPGA

“…In addition, the reconfigurable computing implementations using fieldprogrammable gate arrays (FPGAs) combined with parallelization techniques proposed in the literature have shown satisfactory results when compared to systems based on sequential solutions [5], [7]. FPGAs are widely used to implement these algorithms in parallel, as processing time and cost are significantly reduced [8]. The FPGA is an array of reconfigurable logic blocks that allows the implementation of several logic circuits that can operate independently, enabling parallel processing of different data simultaneously [9].…”

High-speed detection of emergent market clustering via an unsupervised parallel genetic algorithm

“…A number of authors have considered parallel architectures to accelerate GAs (see [35,11,18,31,32,5,4,20] as examples). While the work of [20] is conceptually similar to the implementation proposed in this paper, a key difference is our choice of fitness function for the clustering scheme.…”