Using Hardware Performance Monitors to Isolate Memory Bottlenecks

Buck, Bryan; Hollingsworth, Jeffrey K.

doi:10.1109/sc.2000.10034

Cited by 21 publications

(18 citation statements)

References 11 publications

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“…Buck et al use the Itanium-2 data tracing PMU support to associate load misses to source code lines and data structures in uniprocessor programs [Buck and Hollingsworth 2004]. Buck et al also compare different hardware mechanism for detecting uniprocessor memory hierarchy bottlenecks [Buck and Hollingsworth 2000b]. Satoh et al study data-flow techniques to analyze data sharing patterns at compile time for OpenMP programs [Sato et al 1999].…”

Section: Related Workmentioning

confidence: 99%

Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques

Marathe

Mueller

Supinski

2006

ACM Trans. Archit. Code Optim.

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Application performance on high-performance shared-memory systems is often limited by sharing patterns resulting in cache-coherence bottlenecks. Current approaches to identify coherence bottlenecks incur considerable run-time overhead and do not scale.We present two novel hardware-assisted coherence-analysis techniques that reduce trace sizes by two orders of magnitude over full traces. First, hardware performance monitoring is combined with capturing stores in software to provide a lossy-trace mechanism, which is an order of magnitude faster than software-instrumentation-based full-tracing and retains accuracy. Second, selected long-latency loads are instrumented via binary rewriting, which provides even higher accuracy and control over tracing but requires additional overhead.

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Section: Related Workmentioning

confidence: 99%

Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques

Marathe

Mueller

Supinski

2006

ACM Trans. Archit. Code Optim.

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show abstract

“…Buck et al use the Itanium-2 data tracing PMU support to associate load misses to source code lines and data structures in uniprocessor programs [7]. Buck et al also compare different hardware mechanism for detecting uniprocessor memory hierarchy bottlenecks [6]. Satoh et al study dataflow techniques to analyze data sharing patterns at compile time for OpenMP programs [28].…”

Section: Related Workmentioning

confidence: 99%

A hybrid hardware/software approach to efficiently determine cache coherence Bottlenecks

Marathe

Mueller

Supinski

2005

Proceedings of the 19th Annual International Conference on Supercomputing

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High-end computing increasingly relies on shared-memory multiprocessors (SMPs), such as clusters of SMPs, nodes of chipmultiprocessors (CMP) or large-scale single-system image (SSI) SMPs. In such systems, performance is often affected by the sharing pattern of data within applications and its impact on cache coherence. Sharing patterns that result in frequent invalidations followed by subsequent coherence misses create cache coherence bottlenecks with significant performance penalties. Past work on identifying coherence bottlenecks based on tracing memory accesses incurs considerable runtime overhead and does not scale well with increasing problem sizes, which makes it infeasible to use with real-world programs.In this paper, we introduce a novel low-cost, hardware-assisted approach to determine coherence bottlenecks in shared-memory OpenMP applications. We assess the merits of our approach on a contemporary SMP platform. Specifically, we assess the feasibility of lossy tracing to pin-point coherence problems in applications. We evaluate the qualitative and quantitative trade-offs between tracing overhead and accuracy of the generated coherence traffic metrics, correlated to memory access points at the program source level.Our lossy tracing mechanism closely approximates the degree of accuracy of determining coherence misses in full traces for most of the benchmarks we study while reducing run-time execution overhead and trace sizes by one to two orders of magnitude. To the best of our knowledge, this novel method significantly outperforms any of the prior approaches and, for the first time, makes cache coherence analysis feasible for long-running applications.

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“…These facilities could enable presentation of data about cache behavior in terms of program data structures at the source code level. Work reported in [3] has shown that such information can be extremely useful in identifying performance bottlenecks caused by bad cache behavior. In [3], the data were obtained through use of a cache simulator which runs considerably slower than the original application (e.g., by a couple of orders of magnitude) and does not model details such as pipelining and multiple instruction issue.…”

Section: Implications For Papimentioning

confidence: 99%

“…Work reported in [3] has shown that such information can be extremely useful in identifying performance bottlenecks caused by bad cache behavior. In [3], the data were obtained through use of a cache simulator which runs considerably slower than the original application (e.g., by a couple of orders of magnitude) and does not model details such as pipelining and multiple instruction issue. Through use of appropriate hardware support (e.g., as on the Itanium), similar data could be obtained more accurately and efficiently.…”

Section: Implications For Papimentioning

confidence: 99%

A Comparison of Counting and Sampling Modes of Using Performance Monitoring Hardware

Moore¹

2002

Lecture Notes in Computer Science

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Abstract. Performance monitoring hardware is available on most modern microprocessors in the form of hardware counters and other registers that record data about processor events. This hardware may be used in counting mode, in which aggregate events counts are accumulated, and/or in sampling mode, in which time-based or event-based sampling is used to collect profiling data. This paper discusses uses of these two modes and considers the issues of efficiency and accuracy raised by each. Implications for the PAPI cross-platform hardware counter interface are also discussed.

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Using Hardware Performance Monitors to Isolate Memory Bottlenecks

Abstract: In

Cited by 21 publications

References 11 publications

Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques

Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques

A hybrid hardware/software approach to efficiently determine cache coherence Bottlenecks

A Comparison of Counting and Sampling Modes of Using Performance Monitoring Hardware

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