Using hardware performance counters to speed up autotuning convergence on GPUs

Filipovič, Jiří; Hozzová, Jana; Nezarat, Amin; Oľha, Jaroslav; Petrovič, Filip

doi:10.1016/j.jpdc.2021.10.003

Cited by 10 publications

(12 citation statements)

References 41 publications

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“…We used the simulated tuning to analyze the convergence speed of the profile-based searcher proposed in [1] and of the random search. During the analysis, the autotuning is performed in the defined number of iterations.…”

Section: Experimental Design Materials and Methodsmentioning

confidence: 99%

“… The random search is used by default. To test profile-based searcher [1] , the macro USE_PROFILE_SEARCHER has to be set to 1 in the code of the benchmark (in cpp file). The time for autotuning is restricted to a certain value set by macro TUNE_SEC.…”

Section: Experimental Design Materials and Methodsmentioning

confidence: 99%

“…Modified from Filipovič et al. [1] . Device Architecture Released Abbreviation GeForce GTX 680 Kepler 2012 680 GeForce GTX 750 Maxwell 2014 750 GeForce GTX 1070 Pascal 2016 1070 GeForce RTX 2080 Turing 2018 2080 …”

Section: Data Descriptionmentioning

confidence: 99%

“…Modified from Filipovič et al. [1] . Counter (prior Volta) Counter (Volta and newer) dram_read_transactions dram__sectors_read.sum dram_write_transactions dram__sectors_write.sum l2_read_transactions lts__t_sectors_op_read.sum l2_write_transactions lts__t_sectors_op_write.sum tex_cache_transactions l1tex__t_requests_pipe_lsu_mem_global_op_ld.sum local_memory_overhead l1tex__t_sectors_pipe_lsu_mem_local_op_st.sum shared_load_transactions l1tex__data_pipe_lsu_wavefronts_mem_shared_op_ld.sum shared_store_transactions l1tex__data_pipe_lsu_wavefronts_mem_shared_op_st.sum inst_fp_32 smsp__sass_thread_inst_executed_op_fp32_pred_on.sum inst_fp_64 smsp__sass_thread_inst_executed_op_fp64_pred_on.sum inst_integer smsp__sass_thread_inst_executed_op_integer_pred_on.sum inst_misc smsp__sass_thread_inst_executed_op_misc_pred_on.sum inst_compute_ld_st smsp__sass_thread_inst_executed_op_memory_pred_on.sum inst_control smsp__sass_thread_inst_executed_op_control_pred_on.sum inst_bit_convert smsp__sass_thread_inst_executed_op_conversion_pred_on.sum inst_executed smsp__inst_executed.sum issue_slot_utilization smsp__issue_active.avg.pct_of_peak_sustained_active dram_utilization dram__throughput.avg.pct_of_peak_sustained_elapsed

l2_utilization lts__t_sectors.avg.pct_of_peak_sustained_elapsed tex_utilization l1tex__t_requests_pipe_lsu_mem_global_op_ld.avg.pct_of_peak_sustained_active

shared_utilization l1tex__data_pipe_lsu_wavefronts_mem_shared.avg.pct_of_peak_sustained_elapsed

sm_efficiency smsp__cycles_active.avg.pct_of_peak_sustained_elapsed warp_execution_efficiency smsp__thread_inst_execute...…”

Section: Data Descriptionmentioning

confidence: 99%

“… We have developed several autotuning benchmarks in CUDA that take into account performance-relevant source-code parameters and reach near peak-performance on various GPU architectures. We have used them during the development and evaluation of a search method for tuning space proposed in [1] . With our framework Kernel Tuning Toolkit, freely available at Github, we measured computation times and hardware performance counters on several GPUs for the complete tuning spaces of five benchmarks.…”

mentioning

confidence: 99%

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Searching CUDA code autotuning spaces with hardware performance counters: data from benchmarks running on various GPU architectures

et al. 2021

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Section: Experimental Design Materials and Methodsmentioning

confidence: 99%

Section: Experimental Design Materials and Methodsmentioning

confidence: 99%

Section: Data Descriptionmentioning

confidence: 99%

l2_utilization lts__t_sectors.avg.pct_of_peak_sustained_elapsed tex_utilization l1tex__t_requests_pipe_lsu_mem_global_op_ld.avg.pct_of_peak_sustained_active

shared_utilization l1tex__data_pipe_lsu_wavefronts_mem_shared.avg.pct_of_peak_sustained_elapsed

sm_efficiency smsp__cycles_active.avg.pct_of_peak_sustained_elapsed warp_execution_efficiency smsp__thread_inst_execute...…”

Section: Data Descriptionmentioning

confidence: 99%

mentioning

confidence: 99%

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Searching CUDA code autotuning spaces with hardware performance counters: data from benchmarks running on various GPU architectures

et al. 2021

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Predicting number of threads using balanced datasets for openMP regions

et al. 2022

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Incorporating machine learning into automatic performance analysis and tuning tools is a promising path to tackle the increasing heterogeneity of current HPC applications. However, this introduces the need for generating balanced datasets of parallel applications’ executions and for dealing with natural imbalances for optimizing performance parameters. This work proposes a holistic approach that integrates a methodology for building balanced datasets of OpenMP code-region patterns and a way to use such datasets for tuning performance parameters. The methodology uses hardware performance counters to characterize the execution of a given region and correlation analysis to determine whether it covers an unique part of the pattern input space. Nevertheless, a balanced dataset of region patterns may become naturally imbalanced when used for training a model for tuning any specific performance parameter. For this reason, we have explored several methods for dealing with naturally imbalanced datasets for finding the appropriated way of using them for tuning purposes. Experimentation shows that the proposed methodology can be used to build balanced datasets and that such datasets, plus a combination of Random Forest and binary classification, can be used to train a model able to accurately tune the number of threads of OpenMP parallel regions.

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