Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield

Abstract

In this work, we use statistical concepts to evaluate the joint probability distribution of manufacturing and test parameters and estimate the future trend of wafer test yield. Owing to the difference between the development speeds of testing technology and manufacturing technology, the testing capability of wafers is far behind the manufacturing capability of the semiconductor. Therefore, with the advancement in technology, the test yield loss caused by the tester inaccuracy has become an important problem. In this article, we propose an enhanced integrated circuit (IC) test scheme (ITS) that uses multiplex testing to improve test quality and test pass rate by retesting, and we rely on the cost evaluation mechanism to obtain the best test and the best profit. Furthermore, the International Roadmap for Devices and Systems (IRDS) 2017 data are used to estimate future test yield trends, and the results prove that the enhanced test scheme (ETS) can effectively estimate the best retest time to obtain the best test yield and the best profit.

Arduino based 74-series integrated circuits testing system at gate level

“…The major goal of the logic integrated circuits (ICs) functional tester research is to build a straightforward, reasonably priced system that can test logic IC functionality for fabrication, laboratory, or maintenance applications with the ability to update the database [9], [10]. The system has a user-friendly communication interface, which enables people without programming experience to create tests and utilize the system rapidly and effectively [11].…”

Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect

“…Therefore, we propose repeating the test method (three-repetition tests scheme, TRTS) in pursuit of high-quality production methods. Using the ATE (automated test equipment) with poor performance, changing the test method, and moving the test guardband (TGB) [15][16][17][18][19][20][21], repeatedly find a truly zero-defect and reliable product to ensure that the chip can function normally and consistently. We referred to the IRDS (International Roadmap for Devices and Systems 2021) data [22] sheet to estimate the future test yield distribution.…”