Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors

Santana, Gustavo M.; Paim, Guilherme; Rocha, Leandro M. G.; Neuenfeld, Renato; Fonseca, Mateus Beck; Costa, Eduardo; Bampi, Sérgio

doi:10.1109/icecs.2017.8292075

Cited by 6 publications

(2 citation statements)

References 15 publications

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“…Here we extend our prior work in [43], investigating the area and power efficiency of our new split-radix butterfly proposal in the whole FFT architecture. In contrast to the related work, we also show how the FFT architectures behave in a real-world scenario by submitting them to a thorough power-estimation methodology, as our Section 4.1 will address.…”

Section: Related Workmentioning

confidence: 78%

“…In contrast to the related work, we also show how the FFT architectures behave in a real-world scenario by submitting them to a thorough power-estimation methodology, as our Section 4.1 will address. It is noticeable in Table 1 that only our previous work in [43] used a detailed synthesis flow to obtain the results as we present here. Finally, none of the related work optimizes the FFT architectures employing the efficient ACs within the split-radix butterfly, as we are herein proposing.…”

Section: Related Workmentioning

confidence: 99%

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Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors

Ferreira

Paim

Rocha

et al. 2021

IET Computers & Digital Tech

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Fast Fourier transform (FFT) is the most common low‐complexity implementation of the discrete Fourier transform, intensively employed to process real‐world signals in smart sensors for the internet of things. Butterflies play a central role as the FFT computing core data path since it calculates complex terms employing several multipliers. A low‐power FFT hardware architecture combining split‐radix decimation‐in‐time butterfly and 5‐2 adder compressors (ACs) is proposed and implemented. The circuits are described in Verilog hardware description language and synthesized using the Cadence Genus synthesis tool. The circuits are mapped onto a 65‐nm CMOS ST standard cell library. Results reveal that the proposed FFT hardware architecture using the split‐radix butterfly is 13.28% more power efficient than the radix‐4 one. The results further show that, by combining 5‐2 AC within the split‐radix butterfly, our proposal saves up to 43.1% of the total power dissipation considering the whole FFT hardware architecture, compared with the state‐of‐the‐art radix‐4 butterfly employing the adder automatically selected by the logic synthesis tool.

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Section: Related Workmentioning

confidence: 78%

Section: Related Workmentioning

confidence: 99%