Using dynamic reconfiguration to implement high-resolution programmable delays on an FPGA

Abstract

Abstract-A digital circuit can be viewed as a network of transistors switching between low and high voltages. These transistors and the wires interconnecting them cause delays in signal propagation. In most cases, designers aim to minimize the delays in order to increase processing speed. Nevertheless, some applications such as delay lines, time to digital converters, asynchronous logic and others require the ability to precisely control a delay between two points in a circuit. This paper proposes a novel way to control the delays in an FPGA by dynamically configuring the routing matrices to build a path with the required delay and to calibrate the delays. Such lowlevel configuration is possible with a dynamic reconfiguration library we developed for Xilinx FPGAs. Our experiments on Virtex-II Pro devices show that any differential delay in a range of 947ps can be reached with a precision of +/-18ps.

FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control

“…In other words, changing circuit fanout requires topological changes to the circuit which in turn needs a new configuration. In [2], a technique is proposed to alter the propagation path length by letting the signal bounce a few times inside the switch matrices of FPGA instead of a direct and straight connection. The concept is illustrated in Figure 2.…”

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

“…In [1], the authors use dynamic reconfiguration to enable fine control over delays in experiments which use a time-to-digital converter (TDC) by manipulating route options through SMs. A fine resolution delay tuning method to improve linearity in TDCs is proposed in [2].…”

Fine resolution delay tuning method to improve the linearity of an unbalanced time‐to‐digital converter on a Xilinx FPGA

“…To the best of our knowledge, only three previous works presented fine delay control (tuning) of routes in FPGAs. In [17], a signal from a LUT is bounced inside a switch matrix (SM) before reaching another LUT. As the number of routes inside the SM is high, the sorted propagation delays of all possible routes vary by fine amounts.…”