Using dynamic cache management techniques to reduce energy in a high-performance processor

Bellas, Nikolaos; Hajj, I.N.; Polychronopoulos, Constantine D.

doi:10.1145/313817.313856

Cited by 61 publications

(26 citation statements)

References 16 publications

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“… A low-power microprocessor the DEC SA-110, dissipates 27% and 16% of the total power, respectively, in the on-chip instruction cache and data cache respectively [29]. Caches clearly present one of the most attractive targets for power reduction, this power reduction in caches can be achieved through several means: semiconductor process improvements, memory cell redesign, voltage reduction, and optimized cache structures [30].…”

Section: A Cachementioning

confidence: 99%

“…For example, a direct mapped 256-byte filter cache achieves a 58% power reduction while reducing performance by 21%, corresponding to a 51% reduction in the energy-delay product over a conventional design [32]. An instruction filter cache or so called level zero cache [30] can be placed between the CPU core and the instruction cache to service the instruction stream. Power savings in instruction fetch result from accesses to a small cache [31].…”

Section: A Cachementioning

confidence: 99%

“…Fig. 4 shows the effect of additional filter cache on the memory organization [30], where parts of the memory hierarchy can be on-chip or off-chip. The filter cache can be more efficiently optimized according to Kin et al [32], who propose a scheme to predict the subsequent fetch addresses at run-time to identify whether the next fetch address is in the filter cache.…”

Section: A Cachementioning

confidence: 99%

See 2 more Smart Citations

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Qadri¹,

Gujarathi²,

McDonald-Maier³

2009

JCP

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Abstract-The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas.

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Section: A Cachementioning

confidence: 99%

Section: A Cachementioning

confidence: 99%

Section: A Cachementioning

confidence: 99%

See 1 more Smart Citation

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Qadri¹,

Gujarathi²,

McDonald-Maier³

2009

JCP

View full text Add to dashboard Cite

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“…• standard cache: level 1 (L1) data cach Table 2 shows the configuration of the caches we sim cache size is closest its typical size [17,24,25] and the other parameters are closest to common ARM XScale processor [26].…”

Section: Simulation Setupmentioning

confidence: 99%

“…A tiny filter cache is positioned behind the processor and the standard L1 data cache to reduce the performance loss. Improvements of this technique has been proposed in [24,[33][34][35].…”

Section: Related Workmentioning

confidence: 99%

Reducing leakage in power-saving capable caches for embedded systems by using a filter cache

Giorgi

Bennati

2007

Proceedings of the 2007 Workshop on MEmory Performance: DEaling With Applications, Systems and Architecture

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Leakage power in data cache memories represents a sizable fraction of total power consumption, and many techniques have been proposed to reduce it. As a matter of fact, during a fixed period of time, only a small subset of cache lines is used. Previous techniques put unused lines, for example, to drowsy state or switch them off completely (cache decay) in order to save power.Our idea is to adaptively select mostly used cache lines. We found that this can be achieved automatically by using a tiny cache acting as a filter "L0" cache. Our main contributions are: i) evaluation of filter cache to reduce leakage; ii) improvement of other existing power-saving techniques; iii) providing results to select the most promising solution.Our experiments, with complete MiBench suite for ARM based processor, show (in average) 10% improvement in leakage saving and 17% in leakage energy-delay versus drowsy-cache; versus decay-cache we found 6% improvement in leakage saving and 13% in leakage energy-delay.

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Energy Management Techniques for SOC Design

Yasuura

Ishihara

Muroyama

Essential Issues in SOC Design

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One of the biggest problems in complicated and high-performance SoC design is management of energy and/or power consumption. In this chapter, we present energy management techniques in system design including HW and SW, SoC architecture and logic design. Dynamic power consumption is the major factor of energy consumption in the current CMOS digital circuits. The dynamic power consumption is affected by supply voltage, load capacitance and switching activity. We present approaches to controlling supply voltage, load capacitance and switching activity dynamically and statically in system architecture and algorithm design levels. We also discuss on the memory architecture for reducing power and energy in HW and SW co-design of SoC. In the future CMOS technology, leakage power consumption becomes dominant, because the threshold voltages are scaled as the transistor size shrinks. We summarize the techniques for reducing leakage power in system architecture design. The contents of the chapter include the following issues;(1) power and energy consumptions in SoC design, (2) tradeoff between energy and performance, (3) tradeoff among energy, QoS (i.e., latency and computational precision), reliability, and flexibility (4) techniques for reducing dynamic power consumption, and (5) leakage power reduction techniques.

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Using dynamic cache management techniques to reduce energy in a high-performance processor

Cited by 61 publications

References 16 publications

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Reducing leakage in power-saving capable caches for embedded systems by using a filter cache

Energy Management Techniques for SOC Design

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