Using algebraic transformations to optimize expression evaluation in scientific code

Zory, Julien; Coelho, Fabien

doi:10.1109/pact.1998.727284

Cited by 11 publications

(8 citation statements)

References 8 publications

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“…While checking the equivalence of two arithmetic expressions, such simplifications are sometimes essential because the scheduler may itself have simplified some arithmetic expressions of the initial behavior [Gupta et al 2000[Gupta et al , 2002Landwehr and Marwedel 1997;Potkonjak et al 1993;Zory and Coelho 1998]. Accordingly, a normalization method and some simplification rules of arithmetic expressions are incorporated in this work.…”

Section: Paths In Fsmdsmentioning

confidence: 99%

Formal verification of code motion techniques using data-flow-driven equivalence checking

Karfa¹,

Mandal

Sarkar

2012

ACM Trans. Des. Autom. Electron. Syst.

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A formal verification method for checking correctness of code motion techniques is presented in this article. Finite State Machine with Datapath (FSMD) models have been used to represent the input and the output behaviors of each synthesis step. The method introduces cutpoints in one FSMD, visualizes its computations as concatenation of paths from cutpoints to cutpoints, and then identifies equivalent finite path segments in the other FSMD; the process is then repeated with the FSMDs interchanged. Unlike many other reported techniques, the method is capable of verifying both uniform and nonuniform code motion techniques. It has been underlined in this work that for nonuniform code motions, identifying equivalent path segments involves model checking of some data-flow properties. Our method automatically identifies the situations where such properties are needed to be checked during equivalence checking, generates the appropriate properties, and invokes the model checking tool NuSMV to verify them. The correctness and the complexity of the method have been dealt with. Experimental results demonstrate the effectiveness of the method.

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Section: Paths In Fsmdsmentioning

confidence: 99%

Formal verification of code motion techniques using data-flow-driven equivalence checking

Karfa¹,

Mandal

Sarkar

2012

ACM Trans. Des. Autom. Electron. Syst.

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“…This technique alleviates performance bottlenecks resulting from control dependences. Algebraic transformations as factorization and extracting multiply-add operation is introduced in [27], however, part of them is executed manually. The algorithm used in this work is based on patternmatching to identify sub-expression of a particular form and rewriting rules, to apply the desired transformation.…”

Section: Related Workmentioning

confidence: 99%

“…The algorithm used in this work is based on patternmatching to identify sub-expression of a particular form and rewriting rules, to apply the desired transformation. Additionally, Zory and Coelho [27] presents some interesting motivations such as applying HR so that an invariant sub-expression can be computed once outside a loop, e.g., replacing…”

Section: Related Workmentioning

confidence: 99%

Combining Height Reduction and Scheduling for VLIW Machines Enhanced with Three-Argument Arithmetic Operations

Abboud

Ben-Asher

Shajrawi

et al. 2012

Int J Parallel Prog

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In here we consider a technique to automatically extract three-argument instructions from sequential arithmetic code. The instructions include: multiply and add, three argument additions and three argument multiplications (MUL3). The proposed solution combines a height reduction technique that generates three-argument instructions and a VLIW scheduling that can benefit from these instructions. The proposed height reduction technique is based on a known theoretical algorithm (MRK) that in some cases can evaluate an algebraic circuit faster than its depth. We modified the MRK algorithm to generate less instructions and emit VLIW instructions. The modified MRK algorithm was implemented in the LLVM compiler and the potential usefulness was measured. Our results show that for arithmetic benchmarks the proposed technique can improve the VLIW scheduling while emitting three-argument instructions. The contribution of this work includes: the modified MRK algorithm as a new technique for height reduction optimizations and the study of the potential usefulness of three-argument instructions. Though our results are for a non existing hardware they show the usefulness of adding such instructions to VLIW CPUs. Note that a previous research showed that MUL3 can be executed as fast as MUL2.

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“…Note that semantic transformations are not new in the polyhedral model. To quote a few, semantic properties of operators are already exploited to recognize algorithms [22] or to extract instruction patterns at source-level [37]. As far as we know, this is the first time that semantic factorizations are used to optimize affine control, while keeping it exact.…”

Section: Introductionmentioning

confidence: 99%

Optimizing Affine Control With Semantic Factorizations

Alias

Plesco²

2017

ACM Trans. Archit. Code Optim.

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Hardware accelerators generated by polyhedral synthesis make an extensive use of affine expressions (affine functions and convex polyhedra) in control and steering logic. Since the control is pipelined, these affine objects must be evaluated at the same time for different values, which forbids aggressive reuse of operators. In this report, we propose an algorithm to factorize a collection of affine expressions without preventing pipelining. Our key contributions are (i) to use semantic factorizations exploiting arithmetic properties of addition and multiplication and (ii) to rely on a cost function whose minimization ensures a correct usage of FPGA resources. Our algorithm is totally parametrized by the cost function, which can be customized to fit a target FPGA. Experimental results on a large pool of linear algebra kernels show a significant improvement compared to traditional low-level RTL optimizations. In particular, we show how our method reduces resource consumption by revealing hidden strength reductions.Key-words: High-level synthesis, polyhedral compilation, affine control, FPGA * CNRS/ENS-Lyon/Inria/UCBL/Université de Lyon † XtremLogic SAS Optimisation du contrôle affine avec des factorisations sémantiques Résumé :Les accélérateurs matériels compilés par les algorithmes de synthèse polyédrique utilisent intensivement des expressions affines (fonctions affines par morceaux, polyèdres convexes) dans leur contrôle. Comme le contrôle est pipeliné, ces objets affines doiventêtreévalués en même temps pour différentes valeurs d'entrée, ce qui interdit une réutilisation aggressive des opérateurs. Dans ce rapport, nous proposons un algorithme pour factoriser une collection d'expressions affines sans empêcher le pipeline. Nos contributions sont (i) l'utilisation de factorisations exploitant les propriétés arithmétiques de l'addition et de la multiplication et (ii) une fonction de coût dont la minimisation assure une utilisation efficace des ressources FPGA. Notre algorithme est totalement paramétré par la fonction de coût, qui peutêtre adaptéeà un FPGA cible donné. Les résultats expérimentaux montrent que notre algorithme complète avantageusement les optimisations RTL bas-niveau implantées dans les outils de synthèse industriels. En particulier, nous montrons comment notre algorithme reduit la taille du circuit en révélant des réductions de force cachées.

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Using algebraic transformations to optimize expression evaluation in scientific code

Cited by 11 publications

References 8 publications

Formal verification of code motion techniques using data-flow-driven equivalence checking

Formal verification of code motion techniques using data-flow-driven equivalence checking

Combining Height Reduction and Scheduling for VLIW Machines Enhanced with Three-Argument Arithmetic Operations

Optimizing Affine Control With Semantic Factorizations

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