Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding

Silveira, Bianca; Abreu, Brunno; Paim, Guilherme; Greller, Mateus; Ferreira, R.; Diniz, Cláudio M.; Costa, Eduardo; Bampi, Sérgio

doi:10.1109/icecs.2017.8292076

Cited by 11 publications

(4 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The proposed FA and 4:2 compressor cells are merged as an 8‐bit subtractor as shown in Figure 2 [40]. In this work, a subtractor consisting of compressors is based on the proposed FA and half adder (HA) design.…”

Section: Proposed Circuitsmentioning

confidence: 99%

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

Sadeghi

Shiri

Rafiee

et al. 2022

IET Circuits, Devices & Syst

View full text Add to dashboard Cite

A new 1-bit full adder (FA) cell illustrating low-power, high-speed, and a small area is presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float techniques. Using the proposed cell, a 4:2 compressor is implemented and its performance is investigated under diverse circumstances of voltage, temperature, and driving. The process and corners are evaluated through the process-voltage-temperature (PVT) variations and the Monte Carlo method (MCM), respectively. The accuracy and reliability of the proposed 4:2 compressor are confirmed carefully. Utilising the proposed FA and the compressor, an efficient 8-bit subtractor is implemented for bioimage processing, in particular for difference detection of images. A new mechanism is presented to improve the detection performance of digital signal processors (DSPs) by the addition and subtraction of two images for their difference. The quality of the resulted image confirms the efficiency of the proposed circuits and the method. The high performance of the circuits makes them a promising candidate for the next generation of integrated circuits (ICs) applicable to medical image processing.

show abstract

Section: Proposed Circuitsmentioning

confidence: 99%

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

Sadeghi

Shiri

Rafiee

et al. 2022

IET Circuits, Devices & Syst

View full text Add to dashboard Cite

show abstract

“…Transpose Buffer (TB) was reported to be more energy-efficient, although it results in greater chip area. The authors in [17], [18] utilized adder/subtractor compressors for butterfly operations and achieved about 10-14% reduction in energy consumption.…”

Section: Introductionmentioning

confidence: 99%

High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding

Partanen

Lemmetti

Sjövall

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

This paper presents the first known high-level synthesis (HLS) implementation for the Sum of Absolute Transformed Differences (SATD) calculation. The proposed hardware architecture is designed for two SATD algorithms: a widespread Fast Walsh-Hadamard Transform (FWHT-SATD) and a recently introduced Transform Exempted scheme (TE-SATD). This 2-stage architecture is made up of two 1-D Walsh-Hadamard Transform (WHT) stages and a transpose buffer (TB) between them. The chosen HLS approach cuts down design time over contemporary design methods and thereby made it feasible to implement a set of dedicated FWHT-SATD and TE-SATD architectures for 4×4, 8×8, and 16×16 pixel blocks. All these six architectures were synthesized for 28 nm and 45 nm standard cell technologies, and their area and energy consumptions were analysed. TE-based implementations provide 6.0-8.3% total cell area savings and 6.9-12.7% better energy-efficiency than traditional FWHT approaches. Our proposal is the first to introduce TE-SATD architectures for up to 16×16 blocks and each of these tailored architectures was shown to provide better trade-off between silicon area and performance than their reference implementations.

show abstract

“…Works in [4] and [5] achieve impressive energy reduction when building adder compressors based SATD architectures, which account for a significant amount of the power dissipated in video encoders.…”

Section: Introductionmentioning

confidence: 99%

Fast Monolithic 8-2 Adder Compressor Circuit

Fontanari

Paim

Rocha³

et al. 2019

JICS

Self Cite

View full text Add to dashboard Cite

Adder compressor architectures have been widely used in multipliers and have recently achieved improvements over conventional approaches in the computation of multiple modules, such as transform blocks, in the context of video coding. This paper reviews four different state-of-the-art 8-2 adder compressor architectures and proposes a novel one. A 65 nm commercial standard cell library was used to synthesize the compressors. The results show that, as a consequence of a shorter critical path, our circuit presented significant improvements regarding maximum operational frequency, while still maintaining similar results for power dissipation. Our circuit also managed to achieve a smaller circuit area, as a result of a more straightforward net interconnection.

show abstract

Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding

Cited by 11 publications

References 5 publications

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding

Fast Monolithic 8-2 Adder Compressor Circuit

Contact Info

Product

Resources

About