Use of simulators for side-channel analysis

Veshchikov, Nikita; Guilley, Sylvain

doi:10.1109/eurosp.2017.31

Cited by 6 publications

(6 citation statements)

References 6 publications

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“…Its drawback is that transistor-level simulators tend to be very slow. Alternatively, researchers have looked at emulating at the source code level [80] and at machine instruction level [67,81]. In source code level emulation, the emulator does not have any information about a specific CPU that will be used to run the compiled machine code of a given source code.…”

Section: Leakage Emulatorsmentioning

confidence: 99%

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Rosita: Towards Automatic Elimination of Power-Analysis Leakage in Ciphers

Shelton¹,

Samwel²,

Batina³

et al. 2021

Proceedings 2021 Network and Distributed System Security Symposium

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Since their introduction over two decades ago, physical side-channel attacks have presented a serious security threat. While many ciphers' implementations employ masking techniques to protect against such attacks, they often leak secret information due to unintended interactions in the hardware. We present ROSITA, a code rewrite engine that uses a leakage emulator which we amended to correctly emulate the microarchitecture of a target system. We use ROSITA to automatically protect a masked implementation of AES and show the absence of exploitable leakage at only a 11% penalty to the performance.

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Section: Leakage Emulatorsmentioning

confidence: 99%

“…Recently, several works have experimented with tools that provide a high resolution emulation of the power consumption [81]. The results of such emulations are combined with standard statistical tests [10] to perform leakage assessment of software without executing it on the actual hardware [67].…”

mentioning

confidence: 99%

Rosita: Towards Automatic Elimination of Power-Analysis Leakage in Ciphers

Shelton¹,

Samwel²,

Batina³

et al. 2021

Proceedings 2021 Network and Distributed System Security Symposium

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“…Achievement: Generic framework for modeling of microarchitectural details in a black-box model. Debande et al [25], the first to point out the significance of deriving realistic leakage models, propose the first gray-box trace [66] 2007 not relevant --power $ Oscar [76] 2009 AT90XX, ATmegaXX --power Debande [25] 2012 not specified --power Gagnerot [31] 2013 Risc-V( not specified) --power SILK [80] 2014 ATmega328P --power SLEAK [82] 2014 ARM Cortex A8 -register access Reparaz [63] 2016 not relevant --power SAVRASCA [81] 2017 ATMega163 -power ASCOLD [61] 2017 ATMega163 -ILA ELMO [55] 2017 ARM Cortex M0 --power ELMO * [73] 2019 ARM Cortex M0 --power ROSITA [73] 2019 ELMO * ARM Cortex M0 power EMSIM [72] 2020…”

Section: A Leakage Detection At Post-silicon Stagementioning

confidence: 99%

“…SAVRASCA [81] uses the tracing feature of the SimulAVR tool and is suitable for the analysis of code for the AtmelAVR family. The simulator can produce both power and execution traces.…”

Section: B Leakage Verification At Post-silicon Stagementioning

confidence: 99%

SoK: Design Tools for Side-Channel-Aware Implementations

Buhan¹,

Batina²,

Yarom³

et al. 2021

Preprint

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“…The reason is that, it is not feasible to isolate the power traces associated to each block from the postsilicon power measurements. Therefore, we could not validate [20] presented a comprehensive survey of simulators for sidechannel analysis, e.g., PINPAS [21], SCARD [22], OSCAR [23], etc. These simulators mostly support software crypto algorithms implemented in microprocessors, not hardware crypto modules.…”

Section: Validation Of Rtl-pscmentioning

confidence: 99%

RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level

Park

Nahiyan

et al. 2019

2019 IEEE 37th VLSI Test Symposium (VTS)

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Power side-channel attacks (SCAs) have become a major concern to the security community due to their noninvasive feature, low-cost, and effectiveness in extracting secret information from hardware implementation of cryto algorithms. Therefore, it is imperative to evaluate if the hardware is vulnerable to SCAs during its design and validation stages. Currently, however, there is little known effort in evaluating the vulnerability of a hardware to SCAs at early design stage. In this paper, we propose, for the first time, an automated framework, named RTL-PSC, for power side-channel leakage assessment of hardware crypto designs at register-transfer level (RTL) with built-in evaluation metrics. RTL-PSC first estimates power profile of a hardware design using functional simulation at RTL. Then it utilizes the evaluation metrics, comprising of KL divergence metric and the success rate (SR) metric based on maximum likelihood estimation to perform power side-channel leakage (PSC) vulnerability assessment at RTL. We analyze Galois-Field (GF) and Look-up Table (LUT) based AES designs using RTL-PSC and validate its effectiveness and accuracy through both gate-level simulation and FPGA results. RTL-PSC is also capable of identifying blocks * inside the design that contribute the most to the PSC vulnerability which can be used for efficient countermeasure implementation.

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Use of simulators for side-channel analysis

Cited by 6 publications

References 6 publications

Rosita: Towards Automatic Elimination of Power-Analysis Leakage in Ciphers

Rosita: Towards Automatic Elimination of Power-Analysis Leakage in Ciphers

SoK: Design Tools for Side-Channel-Aware Implementations

RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level

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