Use Of A Simulation Switch Matrix For Efficient Design Of Cmos Analog Integrated Circuits

Abstract

CMOS analog integrated circuit (IC) design is a technology-dependent process. Analog design follows a process for which transistor sizing is necessary to achieve performance goals that are defined by a series of simulation tests. Both the design and the pedagogical processes make use of one or more algorithms in which a set of subcircuits are separately tested and then linked together into an integrated cell design, usually that of the 8-transistor operational transconductance amplifier (OTA). This paper identifies a technique that reduces much of the extra design overhead by framing the OTA as a single schematic who test configurations are controlled by a simulation version of a switch matrix. The switch matrix (1) links a set of independent sources and loads to the circuit under test and (2) reconfigures the test topology of the circuit. The new technique is of value to both the instruction process and the circuit designer since it is simple and direct. Given the simplicity it is also possible to compare effects of different technologies, usually by a collateral use of a spreadsheet utility and its graph capabilities. The student version of Cadence/ORCAD/pSPICE is the principal simulation design utility, with the Excel platform as a complementary utility.