Upset hardened latch as data synchronizer

An application specific signal processor for gaseous detector systems in high energy physics experiment.

“…One possible option for hardening should be the modification or redesign of the standard cell kit to create a protected final chip using the standard digital flow, the papers from Liu et al (2016), Rockett and Kouba (2008), Cameron et al (2014), Liu et al (2014) deals with hardening by design making its steps to achieve cells for process between 65 nm and 180 nm. Kumari and Mekie (2017) even go further where simulations for upset hardened dual interlocked cell (DICE) in much newer process were addressed including technology nodes of 180 nm, 130 nm, 65 nm and 40 nm for planar devices and 20 nm, 16 nm, 14 nm, 10 nm and 7 nm for fin field effect transistor (FinFET) devices.…”