UNPU: An Energy-Efficient Deep Neural Network Accelerator With Fully Variable Weight Bit Precision

Lee, Jinmook; Kim, Changhyeon; Kang, Sanghoon; Shin, Dayeon; Kim, Sangjin; Yoo, Hoi‐Jun

doi:10.1109/jssc.2018.2865489

Cited by 231 publications

(104 citation statements)

References 12 publications

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“…The comparison is made in terms of performance and the number of memory accesses. UNPU [47] is selected as the representative of the conventional DNN design. The reason for this selection is that UNPU provides a look-up table-based PE (LBPE) to support matrix multiplication and MAC operation.…”

Section: Evaluation Results and Analysismentioning

confidence: 99%

“…However, the performance can be improved by employing other advanced topologies [42] [45], mapping [40], and routing techniques [48]. For the memory bandwidth, we assume that the bandwidth is enough to access 16 bits of data within one cycle (i.e., similar to the assumption in UNPU [47]). With regards to the target DNN networks, we evaluated LeNet [49], MobileNet [50], and VGG-16 [4] as the representative of a small, medium, and large-scale DNN model, respectively.…”

Section: Evaluation Results and Analysismentioning

confidence: 99%

“…In the NoC-based design, however, PEs can communicate with each other through the network, and thus the off-chip memory accesses can be significantly reduced. Moreover, the cache-coherence technique is an important Conventional [47] NoC-based Design LeNet [49] 884,736 47,938 (-94.6%) MobileNet [50] 1,061,047,296 4,360,616 (-99.6%) VGG-16 [4] 1,165,128,192 138,508,072 (-88.1%) aspect in NoC to reduce memory accesses. The data synchronization can be achieved with mature memory-coherent techniques in NoC [51].…”

Section: The Number Of Memory Accessesmentioning

confidence: 99%

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NoC-based DNN accelerator

Chen

Ebrahimi

Wang

et al. 2019

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip

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Deep Neural Networks (DNN) have shown significant advantages in many domains such as pattern recognition, prediction, and control optimization. The edge computing demand in the Internet-of-Things era has motivated many kinds of computing platforms to accelerate the DNN operations. The most common platforms are CPU, GPU, ASIC, and FPGA. However, these platforms suffer from low performance (i.e., CPU and GPU), large power consumption (i.e., CPU, GPU, ASIC, and FPGA), or low computational flexibility at runtime (i.e., FPGA and ASIC). In this paper, we suggest the NoC-based DNN platform as a new accelerator design paradigm. The NoC-based designs can reduce the off-chip memory accesses through a flexible interconnect that facilitates data exchange between processing elements on the chip. We first comprehensively investigate conventional platforms and methodologies used in DNN computing. Then we study and analyze different design parameters to implement the NoC-based DNN accelerator. The presented accelerator is based on mesh topology, neuron clustering, random mapping, and XY-routing. The experimental results on LeNet, Mo-bileNet, and VGG-16 models show the benefits of the NoC-based DNN accelerator in reducing off-chip memory accesses and improving runtime computational flexibility.

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Section: Evaluation Results and Analysismentioning

confidence: 99%

Section: Evaluation Results and Analysismentioning

confidence: 99%

Section: The Number Of Memory Accessesmentioning

confidence: 99%

See 1 more Smart Citation

NoC-based DNN accelerator

Chen

Ebrahimi

Wang

et al. 2019

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip

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“…By considering technology scaling, we see that the energy efficiency (in terms of TOP/s/W) of PPAC is comparable to that of the two fully-digital designs in [23], [24] but 7.9× and 2.3× lower than that of the mixed-signal designs in [6] and [19], respectively, where the latter is implemented in a comparable technology node as PPAC. As noted in Section III-D, mixedsignal designs are particularly useful for tasks that are resilient to noise or process variation, such as neural network inference.…”

Section: B Comparison With Existing Acceleratorsmentioning

confidence: 97%

PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations

Castañeda

Bobbett

Gallyas-Sanhueza

et al. 2019

2019 IEEE 30th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. Most existing PIM architectures are either generalpurpose but only support atomistic operations, or are specialized to accelerate a single task. We propose the Parallel Processor in Associative Content-addressable memory (PPAC), a novel in-memory accelerator that supports a range of matrix-vectorproduct (MVP)-like operations that find use in traditional and emerging applications. PPAC is, for example, able to accelerate low-precision neural networks, exact/approximate hash lookups, cryptography, and forward error correction. The fully-digital nature of PPAC enables its implementation with standard-cellbased CMOS, which facilitates automated design and portability among technology nodes. To demonstrate the efficacy of PPAC, we provide post-layout implementation results in 28nm CMOS for different array sizes. A comparison with recent digital and mixed-signal PIM accelerators reveals that PPAC is competitive in terms of throughput and energy-efficiency, while accelerating a wide range of applications and simplifying development.

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“…However, one of the challenges of the modern machine learning algorithms is their energy dissipation [13]. Most of the machine learning hardware development is done using either standard cell digital design methods [14,15] or mixed-signal methods [16] employing analogue processing techniques in CMOS technologies. The advancement and scaling of CMOS technologies have always been based on improving the performance of digital systems.…”

Section: Introductionmentioning

confidence: 99%

An energy efficient time-mode digit classification neural network implementation

Akgun

Mei

2019

Phil. Trans. R. Soc. A.

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This paper presents the design of an ultra-low energy neural network that uses time-mode signal processing). Handwritten digit classification using a single-layer artificial neural network (ANN) with a Softmin-based activation function is described as an implementation example. To realize time-mode operation, the presented design makes use of monostable multivibrator-based multiplying analogue-to-time converters, fixed-width pulse generators and basic digital gates. The time-mode digit classification ANN was designed in a standard CMOS 0.18 μm IC process and operates from a supply voltage of 0.6 V. The system operates on the MNIST database of handwritten digits with quantized neuron weights and has a classification accuracy of 88%, which is typical for single-layer ANNs, while dissipating 65.74 pJ per classification with a speed of 2.37 k classifications per second. This article is part of the theme issue ‘Harmonizing energy-autonomous computing and intelligence’.

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UNPU: An Energy-Efficient Deep Neural Network Accelerator With Fully Variable Weight Bit Precision

Cited by 231 publications

References 12 publications

NoC-based DNN accelerator

NoC-based DNN accelerator

PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations

An energy efficient time-mode digit classification neural network implementation

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