Universal-V/sub dd/ 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

Osada, Kensuke; Shin, Jinuk Luke; Khan, M.; Liou, Yu-De; Wang, K.; Shoji, K.; Kuroda, Kenichi; Ikeda, Shuji; Ishibashi, Koji

doi:10.1109/4.962296

Cited by 60 publications

(19 citation statements)

References 4 publications

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“…This method, however, does not track the memory BL differential signal development delay well across the process corners. Better tracking has motivated the development of replica-based delay circuits [13][14][15][16]. These designs use a replica element that is designed to match and track the SRAM cell delay, sometimes implemented as an extra array column, which incurs an area cost.…”

Section: Timing Path Control and Previous Workmentioning

confidence: 99%

Reducing process variation impact on replica-timed static random access memory sense timing

2009

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Section: Timing Path Control and Previous Workmentioning

confidence: 99%

Reducing process variation impact on replica-timed static random access memory sense timing

2009

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“…This condition is difficult to preserve across process corners, operating temperatures, and low supply voltages. 12 Finally, a low-power memory that degrades overall bit density in terms of Mbits/mm 2 will increase system cost and potentially reduce the range of applicability because of economic factors. For area efficiency, longer BLs and WLs are chosen.…”

Section: Challengesmentioning

confidence: 99%

Challenges and Directions for Low-Voltage SRAM

Qazi

Sinangil

Chandrakasan

2011

IEEE Des. Test. Comput.

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SRAM IS THE most common embedded-memory option for CMOS ICs. As the supply voltage of lowpower ICs decreases, it must remain compatible with the operating conditions. At the same time, increasingly parallel architectures of such low-power systems demand more on-chip cache to effectively share information across parallel processing units. Finally, supply voltage scaling improves the energy consumed by SRAM and dramatically reduces its leakage power.Achieving low-voltage operation in SRAM faces a confluence of challenges, originating from process variation, and related to bit cell stability, sensing, architecture, and efficient CAD methodologies. The trend toward increased quantity of embedded SRAM in scaled technology compounds the specific need of SRAM in low-power systems. Integrating more memory on chip provides an effective means to use silicon because of memory's lower power density, layout regularity, and performance and power benefits from reduced off-chip bandwidth. As a result, the everincreasing integration of embedded SRAM continues. 2 By employing some of the design innovations discussed in this article, this memory design minimizes energy per access and achieves a 50Â reduction in leakage power by trading off performance. Indeed, low-power systems benefit from SRAMs that function at very low voltage in the state of the art, but such design solutions of lowvoltage SRAM significantly impact area and performance. 3 Reducing this area overhead and further improving the metrics of energy per accessed bit and leakage power will enable new opportunities for low-power electronics in mobile platforms. Wearable electronics, portable medical monitors, and implantable medical devices are some of the applications requiring the storage of significant quantities of information (e.g., patient data), low-access energy caches, and a long operating lifetime from a battery.In this article, we discuss the challenges to embedded-SRAM design, with particular emphasis on the factors that limit the minimum operating supply voltage V min . We also explore various design solutions and discuss open areas of investigation. ChallengesThe workhorse of embedded memory is SRAM based on the 6T (six-transistor) cell, shown in Figure 2a. From this cell, a subarray is assembled by tiling memory cells into a grid with wordlines (WLs) running horizontally and bitlines (BLs) running vertically, as in Figure 3. Each memory cell is associated with one or more WLs and one or more BLs. Nominally, the bit cell supplies and well biases are globally connected to static voltage sources. During read, the WL voltage V WL is raised, and the memory cell discharges either BLT (bitline true) or BLC (bitline complement), depending on the stored data on nodes Q and bQ. A sense amplifier converts the differential signal to a logic-level output. Then, at the end of the read cycle, the BLs return to the positive supply rail. During write, V WL is raised and the BLs are forced to Future Landscape of Embedded MemoriesEditor's note: SRAMs capable of operating a...

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“…Figure 7 illustrates a block diagram of the proposed SRAM to which the optimum voltage control scheme is applied. In the proposed SRAM, a memory cell array is divided into 64 blocks so that one block has 128 words by 8 bits, in which the voltage controls are done by a blockby-block basis since Vdd lines in the memory cells are along with bitlines (BLs) [11] unlike the row-by-row Vdd control [12]. Vdd selectors are implemented in order to change the voltages (Vmc and WL voltage).…”

Section: /√Lw (Au) Standard Deviation Of Vthmentioning

confidence: 99%

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

Morita¹,

Fujiwara²,

Noguchi³

et al. 2006

IEICE Transactions on Fundamentals of Electronics, Communicatio

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SummaryWe propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy wordline and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30% can be achieved at 100MHz. In a 65-nm 64-Mb SRAM, a 74% power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1%, and area overhead is 5.6%.

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Universal-V/sub dd/ 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

Cited by 60 publications

References 4 publications

Reducing process variation impact on replica-timed static random access memory sense timing

Reducing process variation impact on replica-timed static random access memory sense timing

Challenges and Directions for Low-Voltage SRAM

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

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