Universal read/write buffer for multiprocessor cache coherency schemes

Abstract

There are many publications in the area of cache coherence for multiprocessor systems as shared memory proved to be a very effective approach to high speed performance. However, most of the works reported are limited to applications of multiprocessor system using single protocol. As the complexity of the multiprocessor system increases, the demand for using mixed computers in one system is more and more pronounced. In this paper, we present the design and implementation of universal readlwrite bufEer which supports multiprocessor cache coherence of different protocols. Analysis of the approach, hardware description, and algorithm are discussed in details. The complete design has been simulated successllly in VHDL. Our analysis shows that, for given system parameters, the performance of the cache system is improved better than 200% if the universal buffer is used.