Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators

Jeong, Geonhwa; Kestor, Gokcen; Chatarasi, Prasanth; Parashar, Angshuman; Tsai, Po-An; Rajamanickam, Sivasankaran; Gioiosa, Roberto; Krishna, Tushar

doi:10.1109/pact52795.2021.00010

Cited by 12 publications

(2 citation statements)

References 19 publications

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“…COAC is the first framework to support the assessment of the best unrolling combinations across complete neural networks, taking energy, latency and cost jointly into account. These capabilities are currently lacking in state-of-the-art hardware design exploration frameworks in literature, such as ZigZag [8], Timeloop [9] and Union [19], as summarized in Table VIII. In the introduction of this paper, we talked about 3 different approaches to map a convolutional network on a PE array: using a fixed SU for all layers (lowest flexibility), using an optimized SU for each individual layer (highest flexibility) and a hybrid version with a limited number of SUs for the complete network.…”

Section: B Qualitative Comparison With Other Frameworkmentioning

confidence: 99%

COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing

Colleman

Shi

Verhelst

2023

IEEE Trans. VLSI Syst.

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To achieve high accuracy, convolutional neural networks (CNNs) are increasingly growing in complexity and diversity in layer types and topologies. This makes it very challenging to efficiently deploy such networks on custom processor architectures for resource-scarce edge devices. Existing mapping exploration frameworks enable searching for the optimal execution schedules or hardware mappings of individual network layers, by optimizing each layer's spatial (dataflow parallelization) and temporal unrolling (execution order). However, these tools fail to take into account the overhead of supporting different unrolling schemes within a common hardware architecture. Using a fixed unrolling scheme across all layers is also not ideal, as this misses significant opportunities for energy and latency savings from optimizing the mapping of diverse layer types. A balanced approach assesses the right amount of mapping flexibility needed across target neural networks, while taking into account the overhead to support multiple unrollings. This paper, therefore, presents COAC, a cross-layer design space exploration and mapping framework to optimize the flexibility of neural processing architectures by balancing configurability overhead against resulting energy and latency savings for end-to-end inference. COAC does not only provide a systematical analysis of the architectural overhead in function of the supported spatial unrollings, but also builds an automated flow to find the best unrolling combination(s) for efficient end-to-end inference with limited hardware overhead. Results demonstrate that architectures with carefully optimized flexibility can achieve up to 38% EDP (energy-delay-product) savings for a set of six neural networks at the expense of a relative area increase of 9.5%.

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Section: B Qualitative Comparison With Other Frameworkmentioning

confidence: 99%

COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing

Colleman

Shi

Verhelst

2023

IEEE Trans. VLSI Syst.

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“…Interstellar [43] uses Halide [30] to explore DNN accelerator designs. Union [14] uses MLIR programs as inputs to optimize spatial DNN accelerators by analyzing tensor operations expressed in Linalg or Affine dialect with MAESTRO [18] and Timeloop [26] as cost models. Similar to the EQueue methodology, these frameworks benefit from separating modeling from representation for rapid iteration.…”

Section: Related Workmentioning

confidence: 99%

Compiler-Driven Simulation of Reconfigurable Hardware Accelerators

Li¹,

Ye²,

Neuendorffer³

et al. 2022

Preprint

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As customized accelerator design has become increasingly popular to keep up with the demand for high performance computing, it poses challenges for modern simulator design to adapt to such a large variety of accelerators. Existing simulators tend to two extremes: low-level and general approaches, such as RTL simulation, that can model any hardware but require substantial effort and long execution times; and higher-level application-specific models that can be much faster and easier to use but require one-off engineering effort.This work proposes a compiler-driven simulation workflow that can model configurable hardware accelerator. The key idea is to separate structure representation from simulation by developing an intermediate language that can flexibly represent a wide variety of hardware constructs. We design the Event Queue (EQueue) dialect of MLIR, a dialect that can model arbitrary hardware accelerators with explicit data movement and distributed event-based control; we also implement a generic simulation engine to model EQueue programs with hybrid MLIR dialects representing different abstraction levels. We demonstrate two case studies of EQueue-implemented accelerators: the systolic array of convolution and SIMD processors in a modern FPGA. In the former we show EQueue simulation is as accurate as a state-of-the-art simulator, while offering higher extensibility and lower iteration cost via compiler passes. In the latter we demonstrate our simulation flow can guide designer efficiently improve their design using visualizable simulation outputs.

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Building a domain-specific compiler for emerging processors with a reusable approach

Li,

Liu,

Chen

et al. 2023

Sci. China Inf. Sci.

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Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators

Cited by 12 publications

References 19 publications

COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing

COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing

Compiler-Driven Simulation of Reconfigurable Hardware Accelerators

Building a domain-specific compiler for emerging processors with a reusable approach

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