Unified TDDB model for stacked high-k dielectrics

Correlation of Negative Bias Temperature Instability and Breakdown in HfO2/TiN Gate Stacks

“…These positive species degrades the interface and create traps in the interfacial layer as well as in the bulk. This is similar to SiO 2 but the injection probability increases due to lower barrier height of high-k layer during gate injection (17). The identical degradation trend as a function of temperature in Fig.…”

Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs

“…In contrast, high energy electron from the gate can generate hot holes at the interface or at the surface of silicon substrate because HK layer has higher probability of electron injection due to a lower barrier height than that of SiON ( Fig. 10(b)) [7]. As a result, the interfacial layer (IL) is degraded by holes which in turn led to G m degradation.…”

Understanding the Resistive Switching Phenomena of Stacked Al/Al2O3/Al Thin Films from the Dynamics of Conductive Filaments

“…We notice a gradual increase in g with time until CC SET is reached and this is related to continuous trapping of positive charge [9] in the bulk and/or interfaces of Al 2 O 3 (enabled by a PF model with a given Φ level; see Figure 5(b)). It is thought that a high density of trapped positive charge would be able to modify the energy barriers of Al 2 O 3 during tunneling of carriers [9][10][11][12] (see Figure 5(c)), so that g conduction enhances while progressively reducing SET . For dissolution of the conductive filament, large CC RESET = 100 mA is required (producing Joule heating) and this produces a sudden decrease in gate current g which, in this case, is obtained after the first seconds of stressing bias.…”