UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS

Sun, Xun; Boora, Akshat; Pamula, Rajesh; Huang, Chi-Hsiang; Pena-Colaiocco, Diego; Sathe, Visvesh

doi:10.1109/vlsicircuits18222.2020.9162982

Cited by 4 publications

(3 citation statements)

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“…The performance summary of the FR-DLDO and other state-of-the-art FR-DLDOs is shown in Table 1. The proposed FR-DLDO outperforms other state-ofthe-art FR-DLDOs [65], [69] and frequency-referenced buck converter [67] in the regulation range, peak power efficiency, and figure-of-merit (FOM). PDNs and power management techniques have gained prime importance in SoC designs due to the integration of diverse heterogeneous circuits and systems on a single chip, requiring multiple voltage domains and high-quality fast power delivery.…”

Section: ) Results and Measurementsmentioning

confidence: 94%

“…Some synthesized digital LDOs were recently demonstrated with promising performance metrics [71], [72]. In addition to the distributed PDNs, the synthesizable design of UVFR is recently adopted due to its scalability [67]. Moreover, buck-converter-based UVFRs have been also emerging because they are capable of producing multiple voltage outputs with a single voltage only, i.e., single input, multiple output (SIMO).…”

Section: ) Results and Measurementsmentioning

confidence: 99%

“…Furthermore, it should also be noted that UVFRs require F REF only. They eliminate the need of V REF [64]- [67]. Hence, they don't require to use bandgap reference (BGR) circuits.…”

Section: B State-of-the-art Uvfrsmentioning

confidence: 99%

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Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Akram

Hwang

2021

IEEE Access

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Conventional power delivery networks (PDNs) and power management techniques using off-chip power converters with bulky passive components cannot meet the ever-evolving power delivery requirements of high-performance modern system-on-chips (SoCs). In SoCs, heterogeneous components, including multi-core processors and mixed-signals peripheral circuits, require state-of-the-art PDNs to provide high-quality power-on-demand with minimum latency, simultaneously achieving the small-factor, high conversion efficiency, and minimum current consumption. To satisfy these power delivery requirements, various PDNs have been developed over the past decades, such as the conventional architectures using off-chip power converters, architectures using in-package power converters and fully-integrated power converters, and heterogeneous architectures (off-chip power converters and on-chip regulators). This paper reviews these architectural advancements of the PDNs and their advantages and limitations, which leads us to discuss a heterogeneous PDN structure consisting of a highly efficient off-chip switching-mode power converter and multiple highly precise small linear regulators integrated on chip at point-of-load locations. The heterogeneous PDN has been proved one of the most suitable architectures to achieve high-quality finegrained on-chip power delivery and management in SoCs. This paper also discusses unified voltage and frequency regulators (UVFRs), which support dynamic-variation-aware dynamic voltage and frequency scaling (DVFS) for fine-grained power management in multi-core processors. Based on the UVFR, we propose a modified heterogeneous PDN using frequency-referenced digital low-dropout regulators (FR-DLDOs) for more efficient DVFS, eliminating the need for band-gap circuits to provide reference voltages. As an exemplary implementation of FR-DLDO for this PDN, we present an FR-DLDO with a transientboost control, which accelerates the transient response. The transient-boost control is activated dynamically only when an abrupt change happens out of the steady state. The implemented FR-DLDO fabricated in a 40-nm CMOS process outperforms other FR-DLDOs in the figure-of-merit and peak power efficiency while driving 40 mA of load current. INDEX TERMS Power delivery network (PDN); fine-grained power management; dynamic-voltage and frequency scaling (DVFS); dynamic-voltage scaling (DVS); low-dropout regulator (LDO); digital LDO; unified-voltage and frequency regulator (UVFR); frequency-referenced digital LDO (FR-DLDO); transientboost control.

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Section: ) Results and Measurementsmentioning

confidence: 94%