Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network

Gupta, Manav; Oatley, Jarod L.; Joseph, Russ; Wei, Gu-Yeon; Brooks, David

doi:10.1109/date.2007.364663

Cited by 151 publications

(104 citation statements)

References 7 publications

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“…There are two important validation (a) P roc 100 points to observe. First, impedance peaks at around the resonance frequency of 100MHz to 200MHz, which matches a large body of prior work describing typical power delivery network characteristics [1], [2], [8], [24], [25]. Second, the small graph embedded within Fig.…”

Section: A Using Off-the-shelf Componentsmentioning

confidence: 63%

“…Previous descriptions of voltage swings have been done primarily by using either custom voltage transient test (VTT) tool kits [13], [15] or simulation [2], [8], [16]- [18]. These approaches have severe limitations that prevent us from observing the voltage noise characteristics of a real processor as it is running full programs and operating under production settings.…”

Section: A Using Off-the-shelf Componentsmentioning

confidence: 99%

“…2 summarizes the performance degradation associated with margins, showing that a 20% voltage margin in today's 45nm node translates to ∼25% loss in peak clock frequency. 2 A doubling in voltage swing by 16nm implies more than 50% loss in peak clock frequency, owing to increasing circuit sensitivity at lower voltages. Therefore, worst-case operating voltage margins are not sustainable in the long run.…”

Section: Introductionmentioning

confidence: 99%

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Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Reddi

Kanev

Kim

et al. 2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel R Core TM 2 Duo processor. By sensing on-die voltage as the processor runs singlethreaded, multi-threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4%, far from the processor's 14% worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15% to 20% performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing microarchitectural activity that leads to voltage swings within multi-core systems, we show that a voltagenoise-aware thread scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.

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Section: A Using Off-the-shelf Componentsmentioning

confidence: 63%

Section: A Using Off-the-shelf Componentsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Reddi

Kanev

Kim

et al. 2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

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“…The PDN forms a resonant tank that produces impedance peaks at multiple resonant frequencies. The dominant resonance frequency (fres) usually occurs at low-tomiddle frequency range (MHz to 100MHz) [7,8]. Though highperformance chips' working frequencies are much higher than this resonance frequency in general, chip runtime loading frequency is not.…”

Section: Introductionmentioning

confidence: 99%

Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction.

Shi

Xiong

Chen

et al. 2009

2009 Asia and South Pacific Design Automation Conference

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“…Also note that dividing by varying voltage would be unnecessarily pessimistic. This instantaneous current can be related to varying supply voltage through (1) filter techniques that use convolution to relate a history of current consumption to voltage [18], [19], [23] or (2) circuit simulation that directly models the RLC network [24], [25]. In either case, models can be extended to capture higher order power delivery system effects through use of a more complex convolution filter or a detailed circuit model.…”

Section: Mid-frequency Modelsmentioning

confidence: 99%

Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors

et al. 2007

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Power is the source of the greatest problems facing microprocessor designers. High-power processors rapidly deplete battery energy. Rapid changes in power consumption result in on-chip voltage fluctuations that bring transient errors. High spatial and temporal power densities bring high temperatures, which result in decreased lifetime reliability. High temperatures also increase leakage power consumption, thereby closing a self-reinforcing powertemperature feedback loop. The effects of increasing power consumption, power variation, and power density are expensive and distasteful. The wages of power are bulky short-lived batteries, huge heatsinks, large on-die capacitors, high server electric bills, and unreliable microprocessors. The only alternative is optimizing microprocessor power consumption, temperature, and reliability. However, this depends on accurate modeling and rapid analysis of properties that span different disciplines and levels, from device physics, to numerical methods, to microarchitectural design. This article surveys the most important problems brought directly and indirectly by power consumption, indicates the relationships among them, explains recent methods of efficiently modeling them, and indicates promising directions in the ongoing fight against power.

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Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network

Cited by 151 publications

References 7 publications

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction.

Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors

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