Understanding the electrostatics of top-electrode vertical quantized Si nanowire metal–insulator–semiconductor (MIS) structures for future nanoelectronic applications

Dual‐Gate GaAs‐Nanowire FET for Room Temperature Charge‐Qubit Operation: A NEGF Approach

“…[ 18 ] In the current nanowire MOSFET, SiO 2 of 2 nm thickness is selected as the gate insulator since it has been reported to exhibit minimum gate tunneling leakage current in nanoscale MOS architecture. [ 21 ] The source/drain are considered to be GaAs with a doping level of 5 × 10 17 cm −3 since such order of doping concentration is sufficient to make it degenerate. [ 22 ] In order to achieve strong quantum confinement for realizing a one‐level device at room temperature, diameter of the nanowire is taken to be 5 nm and the gate lengths are considered to be 3 nm each, all of which are significantly smaller than the excitonic Bohr radius of GaAs (≈12 nm).…”

Voltage-Tunable Quantum-Dot Array by Patterned Ge -Nanowire-Based Metal-Oxide-Semiconductor Devices

“…Semiconductor quantum dots (QDs) are being regarded as the primary unit for a wide range of advanced and emerging technologies including electronics [1], optoelectronics [2], photovoltaics [3] and biosensing applications [4] as well as the domain of q-bits based quantum information processing [5] It is worthy to mention that Ge is chosen as the semiconductor nanowire material due to its large excitonic Bohr radius and SiO 2 is selected as insulator since it is expected to reduce tunneling leakage significantly due to its larger electron effective mass [7]. On application of a positive bias at the metal terminal of such NWMOS, the electrons are 3-dimensionally confined into the quantum well created at semiconductor/oxide (Ge-NW/SiO 2 ) junction due to: geometrical quantization in two transverse dimensions (i.e.…”