Understanding the Effect of PCB Layout on Circuit Performance in a High-Frequency Gallium-Nitride-Based Point of Load Converter

Abstract

The introduction of enhancement-mode galliumnitride-based power devices such as the eGaN FET offers the potential to achieve higher efficiencies and higher switching frequencies than possible with silicon MOSFETs. With the improvements in switching performance and low parasitic packaging provided by eGaN FETs, the printed circuit board (PCB) layout becomes critical to converter performance. This paper will study the effect of PCB layout parasitic inductance on efficiency and peak device voltage stress for an eGaN FET-based point of load (POL) converter operating at a switching frequency of 1 MHz, an input voltage range of 12-28 V, an output voltage of 1.2 V, and an output current up to 20 A. This paper will also compare the parasitic inductances of conventional PCB layouts and propose an improved PCB design, providing a 40% decrease in parasitic inductance over the best conventional PCB design.

A new family of GaN transistors for highly efficient high frequency DC-DC converters

“…Beyond capacitance, inductance also has a major impact on switching performance [11]. To enable the high switching speed available from the low FOM of GaN transistors, low inductance packaging and printed circuit board (PCB) layout is required.…”

“…The side view, shown in figure 5 illustrates the concept of creating a low profile magnetic field self-cancelling loop in a multilayer PCB structure. By using the optimal layout developed by EPC, GaN based half bridge designs have achieved high frequency loop inductances below 0.4 nH [11], further improving the in-circuit performance of GaN transistors when compared to Si MOSFETs. C. dv/dt Capability As GaN transistors increase the switching speeds capable with a power device they are exposed to significantly higher voltage and current slew rates.…”

Effectively paralleling gallium nitride transistors for high current and high frequency applications

“…The side view, shown in figure 7 illustrates the concept of creating a low profile magnetic field self-cancelling loop in a multilayer PCB structure. By using the optimal layout developed by EPC, GaN based half bridge designs have achieved high frequency loop inductances below 0.4 nH [19], further improving the in-circuit performance of GaN transistors when compared to Si MOSFETs. Combining lower FOM, lower package parasitics, and lower parasitic PCB layouts, GaN transistors provide significant performance benefits over state of the art Si technology.…”

“…The high frequency loop inductance, L Loop , while not as penalizing to switching speeds as common source inductance, still negatively impacts switching performance [18], [19]. Another major drawback of high frequency loop inductance is the drain-to-source voltage spike induced during the switching transition, shown in figure 4, given by: …”

Advanced induction heating appliances using high-voltage GaN gate injection transistors

“…In this paper, the implementation of a series resonant class-D inverter taking advantage of the recently-developed high-voltage Gallium Nitride (GaN) devices [10][11][12][13] is presented, leading to an improved performance, and high frequency and power density implementation with a potential cost-effective implementation compared with other semiconductor technologies [14,15]. The proposed converter can operate at higher switching frequencies, reducing magnetic components size and enabling the design of new and innovative IH processes.…”