Understanding phosphorus diffusion into silicon in a MOVPE environment for III–V on silicon solar cells

Abstract

Dual-junction solar cells formed by a GaAsP or GalnP top cell and a silicon bottom cell seem to be attractive candidates to materialize the long sought-for integration of III-V materials on silicon for photovoltaic applications. When manufacturing a multi-junction solar cell on silicon, one of the first processes to be addressed is the development of the bottom subcell and, in particular, the formation of its emitter.In this study, we analyze, both experimentally and by simulations, the formation of the emitter as a result of phosphorus diffusion that takes place during the first stages of the epitaxial growth of the solar cell. Different conditions for the Metal-Organic Vapor Phase Epitaxy (MOVPE) process have been evaluated to understand the impact of each parameter, namely, temperature, phosphine partial pressure, time exposure and memory effects in the final diffusion profiles obtained. A model based on SSupremlV process simulator has been developed and validated against experimental profiles measured by ECV and SIMS to calculate P diffusion profiles in silicon formed in a MOVPE environment taking in consideration all these factors.

A review of concentrator silicon solar cells

“…Calabrese et al made porous structure on Si substrate to improve the crystalline quality of Ge virtual substrate [102]. Grassman et al grew a GaAsP cell on Si substrate directly using MBE [103], García-Tabarés et al grew a GaP cell on Si substrate directly using metalorganic vapor phase epitaxy (MOVPE) [104] and Wilkins et al grew a GaAs cell on Si substrate which was also made porous structure directly using chemical beam epitaxy [105], but above researchers did not report the efficiencies of the cells, thus it is still hard to grow high quality III-V multi-junction solar cell on Si substrate directly. To overcome the constraints of lattice mismatch between III-V materials and Si in above hetero-epitaxy processes, Derendorf et al used wafer bonding technology to make the three junction GaInP/GaAs/Si cell [106], the efficiency was 23.6% under 71 suns [107].…”

Impact of metal-organic vapor phase epitaxy environment on silicon bulk lifetime for III–V-on-Si multijunction solar cells

“…Although the formation of the emitter by P diffusion can produce excellent minority carrier lifetimes in the base and optimum emitter properties in the Si subcell [18]; we have demonstrated that the effect of long PH 3 exposures at temperatures ranging from 800-875 ºC (required for obtaining a deep enough emitter) will lead to an important degradation of the surface morphology [19]. Of course, a degraded surface morphology will cause deleterious effects on the quality of the subsequent epitaxial growth of III-V layers.…”

“…In particular, in the diffused emitter approach, this process consists of three steps: 1) In the initial stage of the MOVPE process, wafers are typically subjected to a high-temperature annealing under hydrogen (H 2 ) atmosphere to prepare the surface for a high-quality III-V semiconductor epitaxy (oxide pyrolysis, double-step formation, …) [16,17]; 2) in order to form the emitter, wafers are exposed to high-temperature bakes under phosphine (PH 3 ) to enable the diffusion of phosphorus (P) into the silicon substrate [18]; and 3) finally, as a result of the surface degradation caused by the PH 3 exposure during the formation of the emitter, substrates need to be submitted to an additional treatment, aimed to recover the surface morphology for subsequent epitaxial growth [19]. In this sense, the formation of the emitter by exposing wafers to a high PH 3 concentration is followed by a H 2 annealing intended to recover the damaged surface morphology.…”

Optimizing diffusion, morphology and minority carrier lifetime in Silicon for GaAsP/Si dual-junction solar cells

“…On the contrary, when low partial pressures of PH 3 are used (Sample 3), not causing noticeable surface morphology degradation, the P diffusion profiles measured can be simulated without any extra addition of point defects ( In agreement to the previously mentioned morphology deterioration, PH 3 exposure must be minimized for obtaining a smooth Si surface, avoiding excessive Si surface roughness ( Figure 3). However, according to our simulations, the use of weak PH 3 anneals leads to thin emitter, probably prone to show low shunt resistance [15]. Therefore, with the goal of achieving optimal emitter depths, while preserving the surface morphology, an alternative process was proposed.…”