Understanding Performance Gains of Accelerator-Rich Architectures

Fang, Zhenman; Javadi, Farnoosh; Cong, Jason; Reinman, Glenn

doi:10.1109/asap.2019.00013

Cited by 5 publications

(3 citation statements)

References 20 publications

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“…Hardware specialization is the main technique for improving power-performance efficiency in emerging compute platforms. By customizing compute engines, memory hierarchies, and data representations [12,21,43], hardware accelerators provide efficient computation in various application domains like artificial intelligence, image processing, and graph analysis [15, 28-30, 61, 87]. At the same time, there is a growing trend in using domain-specific languages (DSLs) for boosting development productivity, e.g., TensorFlow for deep learning [1], Halide for image processing [59], and GraphIt for graph applications [88].…”

Section: Introductionmentioning

confidence: 99%

Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface

Huang¹,

Lyubomirsky²,

Li³

et al. 2022

Preprint

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Specialized accelerators are increasingly used to meet the power-performance goals of emerging applications such as machine learning, image processing, and graph analysis. Existing accelerator programming methodologies using APIs have several limitations: (1) The application code lacks portability to other platforms and compiler frameworks; (2) the lack of integration of accelerator code in the compiler limits useful optimizations such as instruction selection and operator fusion; and (3) the opacity of the accelerator function semantics limits the ability to check the final code for correctness. The root of these limitations is the lack of a formal software/hardware interface specification for accelerators.In this paper we use the recently developed Instruction-Level Abstraction (ILA) for accelerators to serve this purpose, similar to how the Instruction Set Architecture (ISA) has been used as the software/hardware interface for processors. We propose a compiler flow termed D2A using the ILA and present a prototype that demonstrates this flow for deep learning (DL) applications. This prototype compiles programs from high-level domain-specific languages, e.g., PyTorch and MxNet, to multiple target accelerators with no target-specific extensions to the application or compilerthus demonstrating application portability. It includes compiler optimizations through instruction selection using equality saturation-based flexible matching. Finally, we demonstrate checking the correctness of the resulting code through both formal verification of individual matched operations, as well as fully automated simulation-based validation of complete applications. The evaluation of the prototype compiler is based on six different DL applications and three different accelerators. Overall, this methodology lays the foundation * Equal contribution arXiv, 2022, USA 2022.for integrating accelerators in compiler flows using a formal software/hardware interface.

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Section: Introductionmentioning

confidence: 99%

Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface

Huang¹,

Lyubomirsky²,

Li³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…Recent work [5][6][7][8] shows that CGRAs accompanied with spatial dataflows are well suited to exploit parallelism and are tractable for the mapping of dataflows on the architecture. Furthermore, several researchers have shown that this technology is making further progress with efforts in related areas: DSL and compilers, stream input/output, 9 and architectures, 7 bringing up the relevance of research in the area.…”

mentioning

confidence: 99%

Heterogeneous reconfigurable architectures for machine learning dataflows

Oliveira

Canesche

Reis

et al. 2022

Concurrency and Computation

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This work explores the placement and routing of machine learning applications' dataflow graphs on different heterogeneous coarse‐grained reconfigurable architectures (CGRA). We analyze three different types of processing element (PE) heterogeneity, the first concerning the interconnection pattern, the second being on the kind of operations a single PE can execute, and the last concerning the PE buffer resources. This analysis aim to propose a fair reduction to the overall cost in comparison to the homogeneous CGRA architecture. We compare our results with the homogeneous case and one of the state‐of‐the‐art tools for placement and routing (P&R). Our algorithm executed, on average, 52% faster than VPR 8.1 (Versatile Place and Route), which is an open‐source academic tool designed for the FPGA placement and routing phases, reaching better mapping in 66% of cases and achieving the same results in 26% of cases. Furthermore, a heterogeneous architecture reduces the cost without losing performance in 76% of the cases considering multiplier heterogeneity. We propose a novel heterogeneous buffer architecture that minimizes the buffer resources by 56.3% for K‐means dataflow patterns. We also show that a heterogeneous border chess architecture outperforms a homogeneous one. In addition, our mapping reaches optimal instances of single tree dataflows compared to classical Lee/Choi and H‐trees.

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“…Recent work (Fang et al, 2019;Akbari et al, 2019;Liu et al, 2019b;Weng et al, 2019) shows that CGRAs accompanied with spatial dataflows are well suited to exploit parallelism and are tractable for the mapping of dataflows on the architecture. Furthermore, several researchers have shown that this technology is making further progress with efforts in related areas: DSL and compilers, stream input/output (Nowatzki et al, 2017) and architectures (Liu et al, 2019b), bringing up the relevance of research in the area.…”

Section: Introductionmentioning

confidence: 99%

Design exploration of machine learning data-flows onto heterogeneous reconﬁgurable hardware

Oliveira

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This work explores the placement and routing of Machine Learning applications data- ﬂow graphs on different heterogeneous Coarse-Grained Reconﬁgurable Architectures (CGRA). We analyze three different types of processing element (PE) heterogeneity, the ﬁrst concerning the interconnection pattern, the second being on the kind of ope- rations a single PE can execute, and the last concerning the PE buffer resources. This analysis aims to propose a fair reduction to the overall cost in comparison to the ho- mogeneous CGRA architecture. We compare our results with the homogeneous case and one of the state-of-the-art tools for placement and routing (P&R). Our algorithm executed, on average, 52% faster than VPR 8.1 (Versatile Place and Route), which is an open-source academic tool designed for the FPGA placement and routing pha- ses, reaching better mapping in 66% of cases and achieving the same results in 26% of cases. Furthermore, a heterogeneous architecture reduces the cost without losing performance in 76% of the cases considering multiplier heterogeneity. We propose a novel heterogeneous buffer architecture that minimizes the buffer resources by 56.3% for K-means dataﬂow patterns. We also show that a heterogeneous border chess archi- tecture outperforms a homogeneous one. In addition, our mapping reaches optimal instances of single tree dataﬂows compared to classical Lee/Choi and H-Trees. Keywords: Reconﬁgurable architecture. CGRAs. Placement. Routing.

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Understanding Performance Gains of Accelerator-Rich Architectures

Cited by 5 publications

References 20 publications

Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface

Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface

Heterogeneous reconfigurable architectures for machine learning dataflows

Design exploration of machine learning data-flows onto heterogeneous reconﬁgurable hardware

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