Understanding Co-run Degradations on Integrated Heterogeneous Processors

Zhu, Qi; Wu, Bo; Shen, Xipeng; Shen, Li; Wang, Zhiying

doi:10.1007/978-3-319-17473-0_6

Cited by 4 publications

(3 citation statements)

References 25 publications

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“…Interference within the system consists of memory interference on the shared memory system, and OS scheduling interference on the CPU. The scheduling interference occurs when the Linux scheduler selects an interfering task from the ready queue in favor of the GPU offloading task, which may inject large delays (jitter) into the response time of the offloaded kernel [28]. To protect the offloading point from such jitter, extra synchronizations are inserted around the offload in the OpenMP runtime.…”

Section: Enforcement Of Cpu Memory Inactivitymentioning

confidence: 99%

HePREM: A Predictable Execution Model for GPU-based Heterogeneous SoCs

Forsberg

Benini

Marongiu

2021

IEEE Trans. Comput.

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The ever-increasing need for computational power in embedded devices has led to the adoption of heterogeneous SoCs combining a general purpose CPU with a data parallel accelerator. These systems rely on a shared main memory (DRAM), which makes them highly susceptible to memory interference. A promising software technique to counter such effects is the Predictable Execution Model (PREM). PREM ensures robustness to interference by separating programs into a sequence of memory and compute phases, and by enforcing a platform-level schedule where only a single processing subsystem is permitted to execute a memory phase at a time. This paper demonstrates for the first time how PREM can be applied to heterogeneous SoCs, based on a synchronization technique for memory isolation between CPU and GPU plus a compiler to transform GPU kernels into PREM-compliant codes. For compute bound GPU workloads sharing the DRAM bandwidth 50/50 with the CPU we guarantee near-zero timing varibility at a performance loss of just 59%, which is one to two orders of magnitude smaller than the worst case we see for unmodified programs under memory interference.

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Section: Enforcement Of Cpu Memory Inactivitymentioning

confidence: 99%

HePREM: A Predictable Execution Model for GPU-based Heterogeneous SoCs

Forsberg

Benini

Marongiu

2021

IEEE Trans. Comput.

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“…This section reports two studies that are similar to this work. The first study was done by Zhu et al [36,37] in which the authors studied co-scheduling on an integrated CPU-GPU system and considered a power cap. They devised a greedy algorithm that addressed memory contention from degradation in the execution time perspective while selecting frequency for power capping.…”

Section: Related Work 81 Memory Contention Studiesmentioning

confidence: 99%

Mephesto

Monil

Belviranlı

Lee

et al. 2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

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Integrated shared memory heterogeneous architectures are pervasive because they satisfy the diverse needs of mobile, autonomous, and edge computing platforms. Although specialized processing units (PUs) that share a unified system memory improve performance and energy efficiency by reducing data movement, they also increase contention for this memory since the PUs interact with each other. Prior work has investigated performance degradation due to memory contention, but few have studied the relationship of power and energy to memory contention. Moreover, a comprehensive solution that models memory contention for kernel placement on contemporary heterogeneous systems on chip (SoCs) in response to energy and performance has been largely unaddressed. This paper presents MEPHESTO, a novel and holistic approach for managing this balance. The authors characterize applications and PUs in terms of two memory contention factors-time factors and power factors-to achieve the desired trade-off between energy and performance for collocated kernel execution on heterogeneous systems. The authors believe that this investigation is the first to combine all of these factors and present a simple knobbased approach that expresses the target trade-off. The approach is evaluated on a diverse integrated shared memory heterogeneous system with a CPU, GPU, and programmable vision accelerator. By using an empirical model for memory contention that provides up to 92% accuracy, the kernel collocation approach can provide a near-optimal ordering and placement based on the user-defined, energy-performance trade-off parameter. Moreover, the dynamic programming-based heuristics provide up to 30% better energy or 20% performance benefits when compared with the greedy approaches commonly employed by previous studies.

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“…Mekkat et al (2013) analyzed the management policy for the shared last level cache. Zhang et al (2015Zhang et al ( , 2017b studied the co-running behaviors of different devices for the same application, while Zhu et al (2014Zhu et al ( , 2017b) studied co-running performance degradation for different devices for separate applications. Garzón et al (2017) proposed an approach to optimize the energy efficiency of iterative computation on heterogeneous processors.…”

Section: Performance Analysis For Coupled Heterogeneous Processorsmentioning

confidence: 99%

Performance evaluation and analysis of sparse matrix and graph kernels on heterogeneous processors

et al. 2019

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Heterogeneous processors integrate very distinct compute resources such as CPUs and GPUs into the same chip, thus can exploit the advantages and avoid disadvantages of those compute units. We in this work evaluate and analyze eight sparse matrix and graph kernels on an AMD CPU-GPU heterogeneous processor by using 956 sparse matrices. Five characteristics, i.e., load balancing, indirect addressing, memory reallocation, atomic operations, and dynamic characteristics are our major considerations. The experimental results show that although the CPU and GPU parts access the same DRAM, very different performance behaviors are observed. For example, though the GPU part in general outperforms the CPU part, it cannot achieve the best performance in all cases given by the CPU part. Moreover, the bandwidth utilization of atomic operations on heterogeneous processors can be much higher than a high-end discrete GPU.

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Understanding Co-run Degradations on Integrated Heterogeneous Processors

Cited by 4 publications

References 25 publications

HePREM: A Predictable Execution Model for GPU-based Heterogeneous SoCs

HePREM: A Predictable Execution Model for GPU-based Heterogeneous SoCs

Mephesto

Performance evaluation and analysis of sparse matrix and graph kernels on heterogeneous processors

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