Uncorrelated stochastic bitstream generation and arithmetic computations using Cu:ZnO memristors

Boppidi, Pavan Kumar Reddy; Suresh, Bharathwaj; Abhijith, Gopinathan R.; Raj, P. Michael Preetam; Banerjee, Saswata; Kundu, Souvik

doi:10.1016/j.mssp.2021.106355

Cited by 2 publications

(1 citation statement)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…[9][10][11][12] The concept of SC is well known and extensively studied. CMOSbased, [13,14] memristor-based, [15][16][17][18][19] and spintronic-based [20][21][22][23][24] SC architectures have already been demonstrated in the past. However, CMOS-based SC architectures require several hundred transistors to generate s-bits, limiting their area and energy efficiency.…”

Section: Introductionmentioning

confidence: 99%

A Monolithic Stochastic Computing Architecture for Energy Efficient Arithmetic

et al. 2022

View full text Add to dashboard Cite

As the energy and hardware investments necessary for conventional high‐precision digital computing continue to explode in the era of artificial intelligence (AI), a change in paradigm that can trade precision for energy and resource efficiency is being sought for many computing applications. Stochastic computing (SC) is an attractive alternative since, unlike digital computers, which require many logic gates and a high transistor volume to perform basic arithmetic operations such as addition, subtraction, multiplication, sorting, etc., SC can implement the same using simple logic gates. While it is possible to accelerate SC using traditional silicon complementary metal–oxide–semiconductor (CMOS) technology, the need for extensive hardware investment to generate stochastic bits (s‐bits), the fundamental computing primitive for SC, makes it less attractive. Memristor and spin‐based devices offer natural randomness but depend on hybrid designs involving CMOS peripherals for accelerating SC, which increases area and energy burden. Here, the limitations of existing and emerging technologies are overcome, and a standalone SC architecture embedded in memory and based on 2D memtransistors is experimentally demonstrated. The monolithic and non‐von‐Neumann SC architecture occupies a small hardware footprint and consumes a miniscule amount of energy (<1 nJ) for both s‐bit generation and arithmetic operations, highlighting the benefits of SC.

show abstract