Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System

Jeong, Jaeho; Hong, Jaewan; Maeng, Seungryoul; Jung, Chong‐Hun; Kwon, Youngjin

doi:10.1109/micro50266.2020.00051

Cited by 16 publications

(4 citation statements)

References 53 publications

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“…One would also need to keep tracking modified data after the transaction commits to detect dependencies by later regions. Various works extend HTM with enhancements to enable crash-consistency [1,6,7,32]. These works commit a transaction's atomic updates synchronously with respect to the end of the transaction.…”

Section: Hardware Transactional Memory (Htm)mentioning

confidence: 99%

Asap

Abulila

Hajj

Kim

2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Supporting atomic durability of updates for persistent memories is typically achieved with Write-Ahead Logging (WAL). WAL flushes log entries to persistent memory before making the actual data persistent to ensure that a consistent state can be recovered if a crash occurs. Performing WAL in hardware is attractive because it makes most aspects of log management transparent to software, and it completes log persist operations (LPOs) and data persist operations (DPOs) in the background, overlapping them with the execution of other instructions.Prior hardware logging solutions commit atomic regions synchronously. That is, once the end of a region is reached, all outstanding persist operations required for the region to commit must complete before instruction execution may proceed. For undo logging, LPOs and DPOs are both performed synchronously to ensure that the region commits synchronously. For redo logging, DPOs can be performed asynchronously, but LPOs are performed synchronously to ensure that the region commits synchronously. In both cases, waiting for synchronous persist operations (LPO or DPO) at the end of an atomic region causes atomic regions to incur high latency.To tackle this limitation, we propose ASAP, a hardware logging solution that allows atomic regions to commit asynchronously. That is, once the end of an atomic region is reached, instruction execution may proceed without waiting for outstanding persist operations to complete. As such, both LPOs and DPOs can be performed asynchronously. The challenge with allowing atomic regions to commit asynchronously is that it can lead to control and data dependence violations in the commit order of the atomic regions, leaving data in an unrecoverable state in case of a crash. To address this issue, ASAP tracks and enforces control and data dependencies between atomic regions in hardware to ensure that the regions commit in the proper order.Our evaluation shows that ASAP outperforms the state-of-theart hardware undo and redo logging techniques by 1.41× and 1.53×, respectively, while achieving 0.96× the ideal performance when no persistence is enforced, at a small hardware cost (< 3%). ASAP also reduces memory traffic to persistent memory by 38% and 48%, * Ahmed Abulila is currently affiliated with Microsoft Corporation.

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Section: Hardware Transactional Memory (Htm)mentioning

confidence: 99%

Asap

Abulila

Hajj

Kim

2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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“…Also, such modifications can be more errorprone [20,[57][58][59][60][61]67], breaking the failure-atomicity guarantee. To make NVM programming more straightforward and less buggy, multiple studies have presented frameworks that abstract complex low-level techniques [24,33,44,73] and spot potential buggy codes [20,[57][58][59][60][61]67]. On the other hand, this study aims to execute programs without changes, eliminating error-prone modifications with whole-system persistence.…”

Section: Whole-system Persistence: Design Goals 21 Sw-transparent Fai...mentioning

confidence: 99%

Capri

Jeong

Zeng

Jung

2022

Proceedings of the 31st International Symposium on High-Performance Parallel and Distributed Computing

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This paper investigates whole-system persistence (WSP) that ensures hassle-free crash consistency for all programs while simultaneously leveraging both advantages of the non-volatile memory technologies: high-density and in-memory persistence. Despite the promising characteristics, there are two challenges that must be addressed to make WSP a reality. First, programs must be able to resume the execution from where they had a failure. Second, failure recovery must be offered to any program including the OS in a transparent manner while minimizing persistence overheads.To this end, this paper presents Capri, a compiler and architecture co-designed scheme for region-level whole-system persistence. First, the Capri compiler partitions program into a series of regions whose boundaries serve as recovery points. Then, the Capri architecture provides the regions with crash consistency through hardware-based atomic updates. Finally, with the novel interplay between the architecture and the compiler, Capri provides failure atomicity on the cheap, i.e., with 0%, 12.4%, and 9.1% performance overheads for SPEC CPU2017, STAMP, and Splash3 benchmarks, respectively. CCS CONCEPTS• Hardware → Emerging architectures; Emerging languages and compilers.

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“…Unfortunately, it is a challenging problem to ensure correct data cache persistence in a lightweight manner to maintain forward progress. For example, software logging causes serious performance degradation (100-300% slowdown) since each regular store is preceded by the log store, cacheline flush, and store fence [23,24,31,40,66,73,75].…”

Section: Introductionmentioning

confidence: 99%

Enabling Volatile Caches for Energy Harvesting Systems

Zeng,

Choi,

et al. 2022

Preprint

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Energy harvesting systems have shown their unique benefit of ultra-long operation time without maintenance and are expected to be more prevalent in the era of Internet of Things. However, due to the batteryless nature, they suffer unpredictable frequent power outages. They thus require a lightweight mechanism for crash consistency since saving/restoring checkpoints across the outages can limit forward progress by consuming hard-won energy. For the reason, energy harvesting systems have been designed with a non-volatile memory (NVM) only. The use of a volatile data cache has been assumed to be not viable or at least challenging due to the difficulty to ensure cacheline persistence.In this paper, we propose ReplayCache, a software-only crash consistency scheme that enables commodity energy harvesting systems to exploit a volatile data cache. ReplayCache does not have to ensure the persistence of dirty cachelines or record their logs at run time. Instead, ReplayCache recovery runtime re-executes the potentially unpersisted stores in the wake of power failure to restore the consistent NVM state, from which interrupted program can safely resume. To support store replay during recovery, ReplayCache partitions program into a series of regions in a way that store operand registers remain intact within each region, and checkpoints all registers just before power failure using the crash consistency mechanism of the commodity systems. For performance, ReplayCache enables region-level persistence that allows the stores in a region to be asynchronously persisted until the region ends, exploiting ILP. The evaluation with 23 benchmark applications show that compared to the baseline with no caches, ReplayCache can achieve about 10.72x and 8.5x-8.9x speedup (on geometric mean) for the scenarios without and with power outages, respectively.

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Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System

Cited by 16 publications

References 53 publications

Asap

Asap

Capri

Enabling Volatile Caches for Energy Harvesting Systems

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