2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International 2012
DOI: 10.1109/3dic.2012.6262943
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Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

Abstract: Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding and thinning have become key elements in device processing over the past years. While these elements are now mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging. Hence this work focuses on a novel ZoneBOND approach to face these challenges.

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Cited by 29 publications
(6 citation statements)
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“…We have already compared the thinning performance on blanket wafers (no frontside topography) of two materials from Brewer Science: the spin-on ZoneBOND ® 5150 material [3,4] and the BrewerBOND ™ dry film that is laminated onto the carrier wafers prior to bonding [5]. In this paper, we build further on these 2 material performance and we demonstrate their ability to comply with high-topography wafers containing 50µm Cu pillars frontside.…”
Section: Introductionmentioning
confidence: 91%
See 1 more Smart Citation
“…We have already compared the thinning performance on blanket wafers (no frontside topography) of two materials from Brewer Science: the spin-on ZoneBOND ® 5150 material [3,4] and the BrewerBOND ™ dry film that is laminated onto the carrier wafers prior to bonding [5]. In this paper, we build further on these 2 material performance and we demonstrate their ability to comply with high-topography wafers containing 50µm Cu pillars frontside.…”
Section: Introductionmentioning
confidence: 91%
“…This process was already described [3] and implemented for the first time on blanket wafers [3,4]. This step is performed at room temperature in a peel-off type of process in a SUSS DB12T debonder as described in Figure 10.…”
Section: Room-temperature Thin Wafer Debondingmentioning
confidence: 99%
“…ZoneBOND method [8] was employed to do the temporary bonding (TB) in our process flow. Details of integration flow of TB and backside via revealing (BSR) can be found in [9].…”
Section: Tsi Backside Processmentioning
confidence: 99%
“…These vertically stacked chips can be interconnected via through silicon via (TSV) that enables faster performance by shortening interconnection length. While 3D IC provides many advantages over conventional 2D IC, there have arisen new manufacturing and reliability issues, for example, temporary bonding/debonding [3], keep-away-zone of TSV [4], etc. According to recent studies, thermal management among stacked chips becomes serious since IC performance can be affected by the heat generated in neighboring layers [5].…”
Section: Introductionmentioning
confidence: 99%