Ultrathin Strained Si-on-Insulator and SiGe-on-Insulator Created using Low Temperature Wafer Bonding and Metastable Stop Layers

Abstract

A method for fabricating smooth, uniform thickness, low defect density, monocrystalline SiGe alloys and strained Si on any desired substrate was developed, allowing for the creation of SiGe-on-insulator and strained Si-on-insulator. After wafer bonding and layer transfer via either delamination by hydrogen implantation, or back side grinding and Si etching, a selective SiGe etch was used to remove excess material and expose a strained Si stop layer. Recent improvements made to the process include more robust stop layers, low temperature wafer bonding, and improved selective SiGe etching. A major improvement involves the use of metastable films that allow for thicker stop layers. Experimental data for threading and misfit dislocation density for metastable Si layers on Si 0.75 Ge 0.25 virtual substrates is presented. Another improvement is the use of plasma activation prior to wafer bonding, allowing for strong low temperature bonding, while enabling metastable layers to retain their nonequilibrium strain state. Within the context of layer transfer followed by etching, a detailed analysis of SiGe selective etching stopping on strained Si was conducted. An etch consisting of nitric acid and dilute hydrofluoric acid was optimized to yield an acceptable selectively and etch rate, while not creating any pinholes in the exposed stop layer.

Wafer bonding in silicon electronics

“…Strain engineering and material innovations have been identified as the main contributors to the continued performance improvement in CMOS devices. Besides SOI, significant improvements of the performance are obtained by an increased carrier mobility which has been reported for devices fabricated on strained silicon layers (for example [38][39][40]). Combining the advantages of SOI and strained silicon results in strained silicon on insulator (SSOI) substrates merging the properties of both materials.…”

Etch characteristics of Si1−x Ge x films in HNO3:H2O:HF

“…The conventional methods of fabricating sSOI and SGOI are SmartCut TM and wafer bonding with stop layer [3]. In the wafer bonding with stop layer process, selective Si 1x Ge x removal is used to strip excess Si 1x Ge x layer and controllably stop on a strained Si layer.…”

Decoration and preferential etching of crystal defects in silicon materials: influence of metal decoration on the defect etching process

“…In Silicon-On-Insulator (SOI) wafers crystal defects which originate from the Czochralski (CZ) silicon crystal growth process or result from the SOI fabrication process may be harmful to microelectronic devices manufactured on this material [1,2]. Etching solutions such as a dilute Secco etch are used for the delineation of those crystal defects in SOI materials [3].…”

“…[1] was just Secco etched and Ref. [2] and Ref. [3] were annealed without decoration procedure in the copper or lithium tube, respectively, and then Secco etched.…”