UltraScale+ MPSoC and FPGA families

Boppana, Vamsi; Ahmad, Saleh; Ganusov, Ilya; Kathail, Vinod; Rajagopalan, Vidya; Wittig, Ralph

doi:10.1109/hotchips.2015.7477457

Cited by 34 publications

(20 citation statements)

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“…We implemented passthrough kernels which copy pixels from one memory location to another without applying any arithmetic/logical operations. In the FPGA implementation, Xilinx's SDx tool instantiates data movers [36] for each input or output port to transfer data between the memory mapped domain and the stream domain. Table 2 shows that FPGA takes 6.945 ms to copy an entire image (1080p) with 0.41 mJ/frame, while GPU takes 1.298 ms with 0.19 mJ/frame.…”

Section: Benchmarking Approachmentioning

confidence: 99%

Benchmarking vision kernels and neural network inference accelerators on embedded platforms

Qasaimeh

Denolf

Khodamoradi

et al. 2021

Journal of Systems Architecture

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Developing efficient embedded vision applications requires exploring various algorithmic optimization trade-offs and a broad spectrum of hardware architecture choices. This makes navigating the solution space and finding the design points with optimal performance trade-offs a challenge for developers. To help provide a fair baseline comparison, we conducted comprehensive benchmarks of accuracy, run-time, and energy efficiency of a wide range of vision kernels and neural networks on multiple embedded platforms: ARM57 CPU, Nvidia Jetson TX2 GPU and Xilinx ZCU102 FPGA. Each platform utilizes their optimized libraries for vision kernels (OpenCV, VisionWorks and xfOpenCV) and neural networks (OpenCV DNN, TensorRT and Xilinx DPU). For vision kernels, our results show that the GPU achieves an energy/ frame reduction ratio of 1.1-3.2 compared to the others for simple kernels. However, for more complicated kernels and complete vision pipelines, the FPGA outperforms the others with energy/frame reduction ratios of 1.2-22.3. For neural networks [Inception-v2 and ResNet-50, ResNet-18, Mobilenet-v2 and SqueezeNet], it shows that the FPGA achieves a speed up of [2.5, 2.1, 2.6, 2.9 and 2.5] and an EDP reduction ratio of [1.5, 1.1, 1.4, 2.4 and 1.7] compared to the GPU FP16 implementations, respectively.

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Section: Benchmarking Approachmentioning

confidence: 99%

Benchmarking vision kernels and neural network inference accelerators on embedded platforms

Qasaimeh

Denolf

Khodamoradi

et al. 2021

Journal of Systems Architecture

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show abstract

“…We have run the place and route process for the CP circuit for a Zynq Ultrascale+ FPGA [18] using Vivado. Our design occupies less than 0.1% of the FPGA (286 LUTs and 90 flipflops), and can achieve the frequency of 156.25 MHz that we targeted in our implementation; thus, our design can handle a new FRP message every 6.4 nanoseconds.…”

Section: Hardware Implementationmentioning

confidence: 99%

Accurate Congestion Control for RDMA Transfers

Giannopoulos

Chrysos

Mageiropoulos

et al. 2018

2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS)

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High-performance interconnects need congestion control to deal with traffic bursts. In this paper, we propose ACCurate, a congestion control protocol that assigns exact maxmin fair rates to flows, without relying on costly per-flow state inside the network. ACCurate keeps the backlogs outside of the network, protects innocent flows, and promptly recovers the flows' rates after congestive episodes. Comparisons with TCP and PAUSE-only RDMA under datacenter-resembling workloads further show that ACCurate provides up to 10x faster flow completion times. ACCurate relies on simple hardware that can be readily implemented inside switches. In our implementation, the additional circuitry needed in a 16×16 switch occupies less than 2% of FPGA resources.

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“…The FPGA cloud platform used in this design is based on Xilinx Ultrascale+. This kind of FPGA has a large amount of logic and memory resources, strong scalability, which can greatly reduce the delay of data in the calculation and transmission process, improve the design speed [12]. Finally, the design needs to coordinate the management of the processor and the hardware acceleration part.…”

Section: Introductionmentioning

confidence: 99%

A Digital Watermarking Encryption Technique Based on FPGA Cloud Accelerator

2020

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Digital watermarking has the properties such as invisibility and anti-aggression, so the digital watermarking technology has been widely used in copyright protection, information hiding. The watermarking technology takes into account the invisibility and robustness of the watermark by controlling the embedding intensity and position of the watermark mainly in the transformation domain. In this paper, discrete cosine transform (DCT) is adopted to transform the given image from spatial domain to frequency domain for adding watermark information. In order to meet the demands of image watermarking batch processing and cloud processing in the future, this paper optimized the DCT algorithm and the data precision, and successfully deployed the designed accelerator kernel on the FPGA cloud platform to speed up the processing of watermarking. The implementation of data processing based on cloud platform is the development trend of big data era. The cloud platform adopted in this paper is based on the OpenCL heterogeneous architecture combining CPU and FPGA. The cloud-based implementation makes digital watermarking application highly extensible, widely shareable, and more secure. The whole system implements a series of complete cloud processes including image decoding, image preprocessing, watermark embedding, and watermarked image encoding. The watermarking algorithm is accelerated by the efficient parallel computing capabilities of FPGA. It can be seen that the result of acceleration is remarkable, providing the state-of-the-art throughput of 1.676 GBps and the highest processing speed of 937 FPS for 800 × 800 sized colorimage. INDEX TERMS Cloud services, parallel operation, integer DCT, data encryption and watermarking, heterogeneous architecture.

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UltraScale+ MPSoC and FPGA families

Cited by 34 publications

References 0 publications

Benchmarking vision kernels and neural network inference accelerators on embedded platforms

Benchmarking vision kernels and neural network inference accelerators on embedded platforms

Accurate Congestion Control for RDMA Transfers

A Digital Watermarking Encryption Technique Based on FPGA Cloud Accelerator

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