ULTRARAM™: a low-energy, high-endurance, compound-semiconductor memory on silicon

Abstract

ULTRARAM™ is a non-volatile memory with the potential to achieve fast, ultra-low-energy electron storage in a floating gate accessed through a triple-barrier resonant tunnelling heterostructure. Here we report the implementation of ULTRARAM™ on a Si substrate; a vital step towards cost-effective mass production. Sample growth was carried out using molecular beam epitaxy, by first depositing an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III-V memory epilayers. Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10-ms duration program/erase pulses of ~2.5 V, a remarkably fast switching speed for 10- and 20-µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of the devices revealed retention in excess of 1000 years and degradation-free endurance of over 107 program/erase cycles, exceeding very recent results for similar devices on GaAs substrates.

Simulations of resonant tunnelling through InAs/AlSb heterostructures for ULTRARAM™ memory

“…The remarkable performance characteristics of ULTRARAM™ are predicted by detailed simulations of quantum transport [7], and encouraging results have been demonstrated in single devices and 2 × 2 arrays at room temperature on GaAs substrates at 20 µm gate lengths [8], with implementation on Si substrates on-going [9]. Moreover, recent experimental results validate our previous simulation work, including the proposed half-voltage architecture for random access memory (RAM) applications [10].…”

“…We conclude that this is not part of the ULTRARAM™ tunnelling mechanism and is an artefact of the simulation construction. Indeed, experimental studies support this assertion [8][9][10]19]. The peaks occurring at higher voltages are the expected resonant tunnelling peaks (figures 3(b) and (c)).…”

“…Lastly, is the sharpness of the onset of the peaks; a significant tunnelling current away from the P/E peak voltage will also cause logic disturbances [7]. It can be seen in figure 3 that the resonant tunnelling current forms sharp peaks at a little over 1 V, indicating that the TBRT structure is highly suitable for the implementation of FG memory, as demonstrated in experimental work to date [5,[8][9][10]. The simulations are repeated under the same conditions for each of the structures listed in table 1 for the program cycle, and are shown in figure 4.…”

“…Electrons which tunnel into the FG are trapped there indefinitely by the 2.1 eV barrier on one side (InAs/AlSb heterojunction), and an oxide gate dielectric with a high energy barrier on the other. In previous works [8][9][10], we have used 15 nm of Al 2 O 3 , providing an electron barrier of 3.1 eV [11], and requiring a gate voltage of 2.5 V to initiate P/E tunnelling through the TBRT structure. The choice of gate dielectric is somewhat arbitrary and can be tuned to give the desired memory performance.…”

“…Indeed, thicknesses could be offset across the entire growth due to imprecise calibration, or vary across the wafer. This is of particular concern for the commercial development of ULTRARAM™, as it is vital that the InAs/AlSb heterostructures currently grown on 3 ′′ Si [9] be transferred onto 12 ′′ Si substrates in order to be cost-competitive. In this work, we present non-equilibrium Green's function (NEGF) simulations of the ULTRARAM™ resonant tunnelling region, where layer thicknesses are varied to investigate the effect on the performance of the memory.…”