Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches

Yoshida, Hayato; Shiotsu, Yusaku; Kitagata, Daiki; Yamamoto, S.; Sugahara, Satoshi

doi:10.1109/ojcas.2021.3104945

Cited by 4 publications

(11 citation statements)

References 36 publications

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“…During the ULVR mode, the dual-mode inverters in the cell act as a ST inverter having rectangular-shaped transfer characteristics with wide hysteresis, and thus the ULVR-SRAM can stably retain data even at VUL (= ~0.2 V). Since the ULVR mode can effectively reduce the standby power [20], substantive PG using the ULVR mode can be achieved. This ST mode of the dual-mode inverters can be also applied to the stable energy-efficient SRAM EMP operation.…”

Section: Related Workmentioning

confidence: 99%

“…The SRAM Norm operation can be performed using the normal inverter mode of the dual-mode inverters. High-performance SRAM operations comparable to conventional 6T-SRAM operations can be achieved at the ordinary supply-voltage VDD (VUL < VEMP < VDD) [20], [21]. Therefore, the ULVR-SRAM is promising for PIM-type NN accelerators.…”

Section: Related Workmentioning

confidence: 99%

“…In our previous paper [20], the ULVR-SRAM cell was designed to achieve the two-mode operations of the SRAM Norm and ULVR modes, particularly, to achieve efficient standby power reduction during the ULVR mode. Thus, this cell employed the header-and footer-power-switches (HFPSs).…”

Section: Related Workmentioning

confidence: 99%

“…Fig. 1(a) shows the circuit configuration of the ULVR-SRAM cell that is comprised of the dual-mode inverters with the pMOS feedback transistors (FBTs) [20]. The storage nodes are denoted by Q and Q′ in the figure.…”

Section: A Ulvr-srammentioning

confidence: 99%

“…The bias VFB of the FBTs is controlled by the control switches (CSs) cell 1 CS and cell 2 CS . VFB is set to VFBM (= 0.4 V) for the SRAM EMP mode and to VFBL (= 0.2 V) for both the SRAM Norm and ULVR modes [20]. As (VVDD, VFB) = (VDDH, VFBL), the dual-mode inverters in the cell operate with the normal inverter mode, and thus the SRAM Norm operation can be achieved.…”

Section: A Ulvr-srammentioning

confidence: 99%

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Binarized Neural Network Accelerator Macro Using Ultralow-Voltage Retention SRAM for Energy Minimum-Point Operation

Shiotsu

Sugahara

2022

IEEE J. Explor. Solid-State Comput. Devices Circuits

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A binarized neural network (BNN) accelerator based on a processing/computing-in-memory architecture using ultralow-voltage retention SRAM (ULVR-SRAM) is proposed for the energy minimum-point (EMP) operation. The BNN accelerator (BNA) macro is designed to perform stable inference operations at EMP and substantive power-gating using ULVR at an ultralow voltage (< EMP), which can be applied to fullyconnected layers with arbitrary shapes and sizes. The EMP operation of the BNA macro, which is enabled by applying the ULVR-SRAM to the macro, can dramatically improve the energy efficiency (TOPS/W) and significantly enlarge the number of parallelized multiply-accumulate (MAC) operations. In addition, the ULVR mode of the BNA macro, which also benefits from the usage of ULVR-SRAM, is effective at reducing the standby power. The proposed BNA accelerator macro can show a high energy efficiency of 65 TOPS/W for fully connected layers. This BNA macro concept using the ULVR-SRAM can be expanded to convolution layers, where the EMP operation is also expected to enhance the energy efficiency of convolution layers.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: A Ulvr-srammentioning

confidence: 99%

Section: A Ulvr-srammentioning

confidence: 99%

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