Ultralow-Power Digital Control and Signal Conditioning in GaAs MMIC Core Chip for X-Band AESA Systems

GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips

“…The state-of-the-art overview is reported in Table 1. Along with the number of bits, the designation of the bits within the core-chip is reported, when available: clearly, most of the bits are used for the phase and amplitude control, while, depending on the chip functionalities, up to six bits [15] are adopted for the switches. It is worth to note than in several cases [16][17][18][19] a serial output bit is also available, allowing to connect more CCs in daisy chain and configure them sequentially, and/or to test/monitor the SIPO output.…”

“…This choice is surely the most convenient in terms of design effort and modularity, since, once the DFF cell is optimized, it is just replicated 2n times to create the two n-bit registers. However, in order to reduce the overall transistor count, hence reducing chip area occupation and improving yield, the HR can be implemented with simple D-type latches in place of flipflops as in [15,19,28]. Since latches are sensitive to levels rather than transitions, in order to adopt this solution the load command must be given in the form of a short enable pulse rather than a transition as discussed in Section 6.…”

“…Both architectures require additional source followers and level-shifting diodes, thus making the circuit very complex and hence not well suited for highly integrated MMICs [22]. On the contrary, if a differential approach is exploited at flip-flop level, adopting a differential flip-flop structure driven by both true and complementary data and clock signals, an optimum trade-off among noise margin, transistor count and power consumption can be achieved [15,18,39]. For more details on the various logic families, the reader can refer to [9,14,22,33] and references therein.…”

“…Another issue, highlighted in [15,39], is that PDKs model typically does not allow interchanging the role of drain and source terminals, i.e., the model is asymmetrical. In some cases, e.g., in processes with field plate, this asymmetry is mandatory, but more often is just added for convenience, since in microwave circuits the role of these two terminals is always distinct and defined a priori (even, in some models the source terminal is internally grounded and not available to the user).…”

“…On the contrary, for digital circuits very small devices, with one finger only and few microns of gate-width, are adopted, which are fully symmetrical, with the role of the drain and source terminals defined instantaneously by the operating conditions. To overcome these issue ad hoc extracted models can be used as done in [24] or in [15] using, respectively, the TriQuint's Own Model (TOM) [41] and a simplified symmetrical Angelov model [42], both suitable for transient simulations. In both cases the ad hoc models have been fitted starting from the simulations results obtained with the original PDK models, accounting for DC and transient characteristics and for scattering parameters.…”