Ultrahigh-Density 3-D Vertical RRAM With Stacked Junctionless Nanowires for In-Memory-Computing Applications

Bringing uncertainty quantification to the extreme-edge with memristor-based Bayesian neural networks

“…Bayesian neural networks excel in relatively small-data regimes, where strong uncertainty is present: they are not large networks, making device overhead bearable. Currently-developed resistive memories integrated in three dimensions may be particularly suitable to our architecture, which features multiple devices per synapse 40 .…”

Ultra‐Confined Catalytic Growth Integration of Sub‐10 nm 3D Stacked Silicon Nanowires Via a Self‐Delimited Droplet Formation Strategy

“…The advantages of a direct growth formation of such tiny SiNW channels, instead of etching, are manifold: First, this additive growth can help to avoid the top-down etching damages to the ultrathin channels; Second, a parallel growth of multiple vertically stacked SiNWs provides the beneficial channels for building the most advanced gate-all-around field effect transistors (GAA-FET, to be adopted in <5 nm technology nodes), as depicted schematically in Figure 1a-c, which can help to maximize the gate-channel capacitive coupling and achieve a much stronger electrostatic control [2,[17][18][19] compared to the fin-gated FET [20,21] in use for <22 nm Node; Third, the low temperature catalytic growth (<450 °C) of SiNWs can be carried out upon foreign amorphous substrates, without the need of preexisting c-Si wafer as substrate, making it a promising candidate to achieve a monolithic 3D integration of multilayers of logic and memory units within a given footprint area, to push further the scaling limit [22][23][24] or implement more advanced neuromorphic and memory-in-computing functionalities. [25][26][27] Built upon our previous works, [28][29][30] demonstrating the possibility of growing parallel SiNWs upon the vertical sidewall grooves via an indium (In) droplet-mediated in-plane solidliquid-solid (IPSLS) mechanism, [31][32][33][34][35] we here develop a new self-delimited growth control strategy, which enables an ultraconfined and uniform growth of 3D stacked SiNW array, and thus an aggressive reduction of the width and height of the SiNW channels to W nw = 9.9 ± 1.2 nm (down to 8 nm) and H nw = 18.8 ± 1.8 nm, respectively, on par with the CD control in 10 nm node. The key growth control parameters and the potential of channel cross-section engineering via a convenient groove profile design are also investigated and discussed.…”

“…The advantages of a direct growth formation of such tiny SiNW channels, instead of etching, are manifold: First, this additive growth can help to avoid the top‐down etching damages to the ultrathin channels; Second, a parallel growth of multiple vertically stacked SiNWs provides the beneficial channels for building the most advanced gate‐all‐around field effect transistors (GAA‐FET, to be adopted in <5 nm technology nodes), as depicted schematically in Figure a–c, which can help to maximize the gate‐channel capacitive coupling and achieve a much stronger electrostatic control [ 2,17–19 ] compared to the fin‐gated FET [ 20,21 ] in use for <22 nm Node; Third, the low temperature catalytic growth (<450 °C) of SiNWs can be carried out upon foreign amorphous substrates, without the need of preexisting c‐Si wafer as substrate, making it a promising candidate to achieve a monolithic 3D integration of multilayers of logic and memory units within a given footprint area, to push further the scaling limit [ 22–24 ] or implement more advanced neuromorphic and memory‐in‐computing functionalities. [ 25–27 ]…”

Improved Ferroelectricity and Endurance of Hf0.5Zr0.5O2 Thin Films in Low Thermal Budget with Novel Bottom Electrode Doping Technology

“…To develop a low cost, energy‐efficient artificial intelligence (AI) computing platform, new information processing approaches, such as in‐memory‐computing (IMC) and near‐memory‐computing (NMC), have been extensively explored to overcome high data latency and high power consumption due to the limited bandwidth between conventional memory and the processor with von Neumann architecture. [ 1,2 ] A series of new material‐based memory devices, such as resistive‐RAM, magnetic‐RAM, and ferroelectric‐RAM, and a number of novel integration methods, such as through silicon vias (TSV)‐based 3D integration and M3D integration have been implemented to greatly enhance the performance and energy‐efficiency of hardware in IMC or NMC. [ 2–4 ] Combining novel ferroelectric memory devices with M3D integration is expected to provide a revolutionary approach to achieve high performance and low power‐consumption IMC or NMC integrated circuits (ICs) with high‐bandwidth data communication ability and highly reduced chip area.…”