Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology

Flatresse, Philippe; Giraud, B.; Noël, Jean-Philippe; Pelloux-Prayer, Bertrand; Giner, F.; Arora, D.; Arnaud, F.; Planes, N.; Coz, Julien Le; Thomas, Olivier; Engels, Sylvain; Cesana, Giorgio; Wilson, Robin; Urard, Pascal

doi:10.1109/isscc.2013.6487798

Cited by 51 publications

(17 citation statements)

References 3 publications

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“…The Ultra-Thin Body and Box (UTBB) FDSOI technology is very much tailored to implement such energy-efficient UWVR circuits [1]. The low electrical parameters variability and reduced short-channel effects enable this technology to offer both a lower minimum operating voltage and better performance at low voltage than same node Bulk technology [1].…”

Section: Motivationmentioning

confidence: 99%

“…The low electrical parameters variability and reduced short-channel effects enable this technology to offer both a lower minimum operating voltage and better performance at low voltage than same node Bulk technology [1]. However, UWVR circuits in FDSOI are usually made using Low Threshold Voltage (LVT) transistors for keeping good performance at low voltage, at the expense of leakage power.…”

Section: Motivationmentioning

confidence: 99%

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Single-well design in FDSOI technology: Towards energy-efficient ultra-wide voltage range digital circuits

Valentian

Thonnart

Pelloux-Prayer

et al. 2015

2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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This paper demonstrates that the Single Well option offered by the FDSOI technology enables to design energy-efficient digital circuits operating on an ultra-wide voltage range. Silicon measurements of a DSP test chip fabricated in the 28nm node show performance ranging from 2.2GHz at 1.3V down to 65MHz at 440mV. Compared to a full LVT implementation, the leakage power is reduced by up to 6x, for a performance penalty of less than 10%. Additionally, balancing the n-MOS/p-MOS trees over this large voltage range only requires a single back-bias voltage, thus simplifying the power management scheme.

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Section: Motivationmentioning

confidence: 99%

Section: Motivationmentioning

confidence: 99%

Single-well design in FDSOI technology: Towards energy-efficient ultra-wide voltage range digital circuits

Valentian

Thonnart

Pelloux-Prayer

et al. 2015

2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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“…Body-biasing is used to modulate threshold voltage (V t ) of transistors. This effect is more pronounced for FDSOI transistors [1], where the change in V t is linear with the amount of body-bias applied. In SRAMs body-biasing can be used to improve read/write margins.…”

Section: Introductionmentioning

confidence: 99%

“…However, certain functionalities can necessitate generating voltages that are higher than V dd . One such example is bodybiasing [1]. It is well-known that the threshold voltage (V t ) of a transistor can be modulated by applying an appropriate body-bias voltage.…”

Section: Introductionmentioning

confidence: 99%

A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency

Biswas

Sinangil

Chandrakasan

2015

IEEE J. Solid-State Circuits

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Abstract-This paper presents a fully integrated, reconfigurable switched-capacitor based step-up DC-DC converter in a 28nm FDSOI process. Three reconfigurable step-up conversion ratios (5/2, 2/1, 3/2) have been implemented which can provide a wide range of output voltage from 1.2V to 2.4V with a nominal input voltage of 1V. We propose a topology for the 5/2 mode which improves the efficiency by reducing the bottomplate parasitic loss compared to a conventional series-parallel topology, while delivering the same amount of output power. Further, the proposed topology benefits from using core 1V devices for all charge-transfer switches without incurring any voltage overstress. The converter can deliver load current in the range of 10 µA to 500 µA, achieving a peak efficiency of 88%, using only on-chip MOS and MOM capacitors for a high density implementation.

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“…Well-known stackedMOSFETs for low-leakage current are thus indispensable. Moreover, the use of fully-depleted SOI MOSFETs [9] is vital for smaller V t -variations. Note that using bulk MOSFETs may be intolerable, considering the standard deviation (σV t ) of the local V t -variation [8] given as σV t = A vt /(LW) 1/2 (A vt ; the Pelgrom coefficient).…”

Section: Introductionmentioning

confidence: 99%

0.5-V 50-mV-swing 1.2-GHz 28-nm-FD-SOI 32-bit dynamic bus architecture with dummy bus

Shaik

Itoh

Amara

2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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Abstract-To achieve a 0.5-V low-power high-speed robust bus, a dynamic bus architecture, combined with a dynamic driver and a dynamic receiver for small leakage current with stacked MOSFETs, is proposed. In particular, the dynamic driver enables high speed even at 0.5 V with increased gateover-drive by changing the power lines from V DD /2 in the standby mode to V DD in the active mode. It further speeds up with the help of another proposal of a dummy bus for tracking the bus-voltage detecting point for reducing the bus swing. Robustness of each proposal is investigated by Monte Carlo simulation. Then, a 0.5-V 28-nm-FD-SOI 32-bit bus architecture using the proposals is evaluated by simulation. The power-supply bounce noise and the reduction are also investigated here through the layout. As a result, it turns out that the architecture has a potential of operating a 1-pF bus at a 50-mV swing, 1.2 GHz, and a standby current of 1.1 μA, with x3-5 faster and more than two-order lower standby current than the conventional static architecture.Keywords-0.5-V 50-mV-swing dynamic bus, stacked MOSFETs, dummy bus, 32-bit dynamic bus architecture

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Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology

Cited by 51 publications

References 3 publications

Single-well design in FDSOI technology: Towards energy-efficient ultra-wide voltage range digital circuits

Single-well design in FDSOI technology: Towards energy-efficient ultra-wide voltage range digital circuits

A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency

0.5-V 50-mV-swing 1.2-GHz 28-nm-FD-SOI 32-bit dynamic bus architecture with dummy bus

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