Ultra-Thin High-K Dielectric Profile Based NBTI Compact Model for Nanoscale Bulk MOSFET

Swami, Yashu; Rai, Sanjeev

doi:10.1007/s12633-018-9984-z

Cited by 13 publications

(9 citation statements)

References 37 publications

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“…The gate bias stress is believed to be the critical characteristic to understand the interface quality of the MOSFET after the thinning process and the presence of defects could lead to a time‐dependent threshold voltage shift. [ 25 ] For n‐channel MOSFETs and/or n‐type thin film transistors, an increase in the positive bias stress (PBS) tends to attract more electrons toward the interface between the channel and the dielectric layer. These electrons are trapped either at low energy level or deep energy level trap states created by oxygen vacancy and oxygen interstitial defects of dielectric at the channel/dielectric interface.…”

Section: Resultsmentioning

confidence: 99%

Ultra‐Thin Chips with Printed Interconnects on Flexible Foils

Kumaresan

Dahiya

et al. 2021

Adv Elect Materials

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“Heterogeneous Integration” is a promising approach for high‐performance hybrid flexible electronics that combine printed electronics and silicon technology. Despite significant progresses made by integrating rigid silicon chips on flexible substrates, the integration of flexible ultra‐thin chips (UTCs) on flexible foils remains a challenge as they are too fragile for conventional bonding methods. Reliable interconnects (low‐resistivity and mechanical robustness) and bonding of UTCs are critical to the realization of hybrid flexible systems. Herein, using a non‐contact printing approach, an easy and cost‐effective method for accessing UTCs on flexible foils is demonstrated. The high‐viscosity conductive paste, extruded from a high‐resolution printer (1–10 µm line width), is used here to connect the metal oxide semiconductor field effect transistors (MOSFETs) on UTCs with the extended pads on flexible printed circuit boards (PCBs). The electrical characterization of MOSFETs, before and after printing the interconnects, reveals an acceptable level of variation in device mobility (change from 780 to 630 cm2 V−1s−1). This is due to the drop in effective drain bias voltage as a marginally small electrical resistance (≈30 Ω) is added by the printed interconnects. The bonded UTCs show robust device performance under bending conditions, indicating high reliability of both the chip thinning and bonding methods.

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Section: Resultsmentioning

confidence: 99%

Ultra‐Thin Chips with Printed Interconnects on Flexible Foils

Kumaresan

Dahiya

et al. 2021

Adv Elect Materials

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“…The natural length (λ), and hence the SCE behavior of the device can be minimized by reducing gate oxide thickness, silicon film thickness, and switching to a high-k gate dielectric, instead of SiO2 [12]- [13]. Furthermore, when the number of gates increases, the natural length decreases.…”

Section: Itc Vandalized Vth Divergence Model Developmentmentioning

confidence: 99%

Proposing an ITC vandalized Threshold Voltage Divergence Model for short channel Omega Gate MOSFET using a partial 3-D Environment

Swami

2022

Preprint

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We present an interface-trapped-charge (ITC) vandalized threshold voltage (VTH) divergence model for omega-gate (Ω-G) MOSFETs using a partial 3-D scaling equation. To account the impact, the model comprises the equivalent number of gates, gate dielectric and silicon film thickness, channel limitations. The impacts of analogous oxide charges on the flat-band voltage are also examined for short-channel-free operation. A thin gate oxide is essential to prevent VTH value divergence caused by the ITC charges. The ITC vandalized device with a thick silicon sheet is altered with wee VTH value variations caused by trapped charges but rapidly increases in the thin silicon sheet device. We can reduce the VTH value by changing the value of oxide-to-gate underlap coverage factor (OUCF). Large underlap coverage factor value is desirable for positive trapped charges and small value for negative trapped charges. A damaged device with negative trapped charges performs better in short-channel conditions than one with positive trapped charges. Due to its 3-D nature, the proposed model may be efficiently used to investigate the VTH behavior and the device operating characteristics of omega-gate (Ω-G) MOSFET. It may also be competently used in device memory cell applications. Hence, the proposed model provides a deep understanding of device physics along with its computational ability, effectiveness and simplicity.

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“…Analytical models for NBT stressing have been researched throughout the years [19][20][21][22][23][24][25][32][33][34][35][36][37]. This model assumes continuous stress on the PMOS devices.…”

Section: Modeling Approachmentioning

confidence: 99%

“…Even though more than 40 years have passed since then, many mechanisms of NBTI are not very well understood yet. In the last decade, many different working groups are addressing NBTI effects, with accent on both description and modeling of voltage threshold shifts [19,20]. Swami presented a model for nano MOSFET for FinFET technologies [20], while Aleksandrov reported a model that is based on a reaction-diffusion principle [21].…”

Section: Introductionmentioning

confidence: 99%

“…In the last decade, many different working groups are addressing NBTI effects, with accent on both description and modeling of voltage threshold shifts [19,20]. Swami presented a model for nano MOSFET for FinFET technologies [20], while Aleksandrov reported a model that is based on a reaction-diffusion principle [21]. Still, an appropriate electrical model to describe instabilities corresponding to different stressing conditions is lacking [22].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method

Mitrović¹,

Danković²,

Ranđelović³

et al. 2020

Informacije MIDEM

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Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide semiconductor (MOS) devices simultaneously exposed to elevated temperature and negative gate voltage. This paper studies threshold voltage shift under static stress associated with the NBT stress induced buildup of both interface traps and oxide trapped charge in the commercial p-channel power VDMOSFETs IRF9520, with the goal to design an electrical model. Change of threshold voltage follow power law t n , where parameter n is different depending on the stressing phase and stressing conditions. Two modeling circuits are proposed and modeling circuit elements values are analyzed. Values of modeling circuits elements are calculated using least square method approximation conducted on obtained experimental results. Modeling results of both circuits are compared with the measured results and then further discussed.

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Ultra-Thin High-K Dielectric Profile Based NBTI Compact Model for Nanoscale Bulk MOSFET

Cited by 13 publications

References 37 publications

Ultra‐Thin Chips with Printed Interconnects on Flexible Foils

Ultra‐Thin Chips with Printed Interconnects on Flexible Foils

Proposing an ITC vandalized Threshold Voltage Divergence Model for short channel Omega Gate MOSFET using a partial 3-D Environment

Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method

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