Ultra‐thin Body Buried In _0.35 Ga _0.65 As Channel MOSFETs with Extremely Low Off‐current on Si Substrates

Abstract

In this paper, we investigated the electrical properties of the Metal‐oxide‐semiconductor gate stack of Ti/Al2O3/InP under different annealing conditions. A minimum interface trap density of 3×1011cm‐2eV‐1 is obtained without postmetallization annealing treatment. Additionally, utilizing Ti/Al2O3/InP MOS gate stack, we fabricated ultra‐thin body buried In0.35Ga0.65As channel MOSFETs on Si substrates with optimized on/off trade‐off. The 200nm gate length device with extremely low off‐current of 0.6nA/μm, and on‐off ratio of 3.3×105, is demonstrated by employing buried low indium (In0.35Ga0.65As) channel with InP barrier/spacer device structure, giving strong potential for future high‐performance and low‐power applications.