Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop

Karimi, Ahmad; Rezai, Abdalhossein; Hajhashemkhani, Mohammad Mahdi

doi:10.1109/tnano.2019.2929233

Cited by 22 publications

(6 citation statements)

References 30 publications

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“…Ultra-low power pulse-triggered carbon nanotube field-effect transistor (CNTFET) based flip-flop is proposed by Karim et al [6] for low power applications. The author used signal feed through technique and also optimized the discharging path to reduce the delay time for the '1' to '0' transition.…”

Section: Related Workmentioning

confidence: 99%

An Improved Power Efficient Clock Pulsed D Flip-flop Using Transmission Gate

Syamala¹,

Muthusamy²

2023

j. of electron. & inf. syst.

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Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption. The proposed work deals with a low-power clock pulsed data flip-flop (D flip-flop) using a transmission gate. To accomplish a power-efficient pulsed D flip-flop, clock gating is proposed. The gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power consumption. The clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called Enable. Due to this process, the clock gets turned off to reduce power consumption when there is no change in the output. The proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is analyzed. The proposed pulsed D flip-flop power consumption is 1.586 µw less than the without clock gated flip-flop. Also, the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the performance. Tanner Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology

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Section: Related Workmentioning

confidence: 99%

An Improved Power Efficient Clock Pulsed D Flip-flop Using Transmission Gate

Syamala¹,

Muthusamy²

2023

j. of electron. & inf. syst.

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“…CNTFETs can extend the validity of Moore's law [17]. Various digital and analog circuits and systems based on CNTFETs have been proposed, such as adders [18][19][20][21], flipflops [22][23][24][25], and multiplexers [26][27][28]. CNTFETs resemble MOSFETs but replace the bulk silicon channel with semiconducting CNTs, as shown in Figure 2.…”

Section: Cntfets and Mosfets Have Similar Structures Butmentioning

confidence: 99%

A Power-Efficient Error Detection and Correction Circuit Design Using Hamming Codes for Portable Electronic Devices

Khan¹,

Shahid²,

Keshari³

et al. 2023

MMEP

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Error-free communication is crucial for modern electronic devices. Error detection and correction mechanisms are essential to ensure accurate information transmission. With the increasing usage of mobile devices and integrated circuits operating at higher speeds, energy efficiency has become an important design consideration. This study presents carbon nanotube field-effect transistor (CNTFET)-based Hamming Error Detection and Correction circuits and compares them with complementary metal-oxide semiconductor (CMOS)-based counterparts in terms of power efficiency and delay. CNTFETs are more power-efficient and faster than CMOS transistors, making them ideal building blocks for logic circuits. The proposed circuits were simulated using HSPICE. Compared with CMOS circuits, the CNTFET designs consumed less power, had lower delays, and smaller power-delay products. The proposed error detection and correction circuits are suitable for power-efficient and portable systems.

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“…The numbers in Figure 3e indicate the count of CNTs and the chiral vector parameters. The gate oxide layer thickness t ox of all CNTFETs and the length of CNTs are set to 5 and 16 nm [13], respectively, to ensure the normal function of the flip‐flop and reduce the total power consumption of the circuit as much as possible.…”

Section: Proposed Cntfet Level‐converting Flip‐flopmentioning

confidence: 99%

Low power design of explicit‐pulsed dual‐edge‐triggered level‐converting flip‐flop based on carbon nanotubes field‐effect transistors

Dai

Yang

Jiang

et al. 2022

Electronics Letters

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Power consumption and performance are the two main concerns in designing pulse‐triggered level‐converting flip‐flops (LCFF). In this letter, through the research on the level conversion circuits, an explicit‐pulsed dual‐edge triggered LCFF based on the carbon nanotubes field‐effect transistors (CNTFETs) is proposed by using the multi‐source voltage technology. The proposed flip‐flop increases the speed by reducing the number of transistors in the charge/discharge path. The characteristics of the CNTFETs are used to obtain transistors with different threshold voltages by changing the chiral vector to optimize the circuit structure and further reduce the power consumption. In addition, the power consumption is further reduced due to the small on‐current of the CNTFETs. The proposed novel structure is simulated in HSPICE using the Stanford model. Simulation results indicate that our proposed flip‐flop reduces 62.9% to 72.4% of power consumption and 73.6% to 89.1% of delay in comparison with other flip‐flops proposed in the references at 50% data switching activity.

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Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop

Cited by 22 publications

References 30 publications

An Improved Power Efficient Clock Pulsed D Flip-flop Using Transmission Gate

An Improved Power Efficient Clock Pulsed D Flip-flop Using Transmission Gate

A Power-Efficient Error Detection and Correction Circuit Design Using Hamming Codes for Portable Electronic Devices

Low power design of explicit‐pulsed dual‐edge‐triggered level‐converting flip‐flop based on carbon nanotubes field‐effect transistors

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