Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM

Circuit Techniques to Assist SRAM Cell: Local Assist Circuitry

“…4.12) results easy implementation of SRAM cell dense layout rules (litho friendly) implementation (Sharma et al 2012). The physical regularity of SRAM layout enables the use of litho optimized specialized DRC rules.…”

“…The SRAM cell type local assist circuitry (Sharma et al 2012) reduces the area overhead and reduces the bit-line parasitic capacitance which reduces the bit-line delay. This map into 1.2 orders of reduction in bit-line delay for 65 nm (Fig.…”

“…Therefore, the litho optimized local assist circuitry results in an overwhelming improvement in the access speed for the scaled voltage levels. (Sharma et al 2012). Column height is 512 cells, 40 nm LP, nominal process corner and 25°C…”

“…The asserted 8T Fig. 4.12 8T SRAM cell type layout of the local assist circuitry:*2x of actual 8T SRAM cell (Sharma et al 2012) SRAM cell discharges the local read bit-line depending on the stored data information. Then the local read buffer is activated by WL_RD signal.…”

“…High bit density based hierarchy (Kushida et al 2009;Sharma et al 2012): alleviates the area overhead issue associated with the use of local assist circuit.…”