Ultra-Low Power Flip-Flops for MTCMOS Circuits

Levacq, David; Dessard, Vincent; Flandre, Denis

doi:10.1109/iscas.2005.1465677

Cited by 12 publications

(5 citation statements)

References 10 publications

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“…This scheme requires extra data-preserving balloon latches and complicated timing for transferring data back and forth between balloon latches and flip-flops on any transition from power down to active mode and vice versa. In [10] David Levacq designed an ultra low power flip-flop using two ultralow leakage diodes and analysis of master slave latches and flip-flops is discussed in [11]. In [12] Linfeng et.al proposes a new transmission gate flip-flop based on dual threshold CMOS technique to reduce it's leakage power.…”

Section: Related Workmentioning

confidence: 99%

Leakage Power Reduction and Analysis of CMOS Sequential Circuits

Rani¹

2012

VLSICS

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A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates.. All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

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Section: Related Workmentioning

confidence: 99%

Leakage Power Reduction and Analysis of CMOS Sequential Circuits

Rani¹

2012

VLSICS

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“…1(c) exhibits Negative-Differential Resistance (NDR) in its reverse I/V characteristic [3][4][5]. Cascading two diodes in reverse with one connected to ground and one to V dd allows us to build a latch with two stable states as illustrated in Fig.…”

Section: Ulp Latch and Srammentioning

confidence: 99%

“…This ULP latch can be used in several applications. First, an MTCMOS flip-flop can be built with the ULP latch for power-gated circuits that need data/state retention [4]. Indeed, traditional flip-flops for data retention are based on a multi-V th design with a fast and leaky low-V th main latch for active operation and a slow low-leakage high-V th shadow/balloon latch for data retention.…”

Section: Ulp Latch and Srammentioning

confidence: 99%

“…The ULP latch in Fig. 7 combines ultra-low leakage down to 3pA with high-speed operation and a reduced transistor count [4]. Second, the ULP latch can be used to build a 7T SRAM cell [5] when combined to an NMOS pass transistor for write access and 2T read buffer, as shown in Fig.…”

Section: Ulp Latch and Srammentioning

confidence: 99%

“…negative (resp. positive) V GS in stand-by mode, thereby pushing I off towards its physical limits [1][2][3][4][5][6][7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

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Disruptive ultra-low-leakage design techniques for ultra-low-power mixed-signal microsystems

Flandre

Bulteel

Gosset

et al. 2011

2011 Faible Tension Faible Consommation (FTFC)

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In this paper, we describe applications of a disruptive ultra-low-leakage design technique for drastically reducing the off current in CMOS mixed analog-digital microsystems without compromising the functional performance. The technique is based on a pair of source-connected n-and p-MOS transistors, automatically biasing the stand-by gate-tosource voltage of the nMOSFET at a negative voltage and that of the pMOSFET at a positive level, thereby pushing the off current towards its physical limits. Playing with gate and drain connections, we have created a family of ULP basic blocks : a 2terminal diode, a 3-terminal transistor and a voltage follower. Using these blocks, we have developed a 7-transistor SRAM cell and an MTCMOS latch with record low stand-by leakage but still high speed performance, highly-efficient power-management units for RF and PV energy harvesting and a microwatt interface for implanted capacitive sensors.Index Terms-Ultra low leakage, Ultra low power, analog and digital CMOS circuits, logic, SRAM, power management, energy harvesting, voltage reference, SOI technology.978-1-61284-647-7/11/$26.00 ©2011 IEEE

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