Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub-$V_{ \rm T}$ Operation

Winstead, Chris; Rodrigues, Joachim Neves

doi:10.1109/tcsii.2012.2231040

Cited by 6 publications

(3 citation statements)

References 27 publications

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“…ECC techniques provided by the hardware vendors significantly increase the power load of HPC-centers. Removing such power-hungry hardware design may be necessary to operate exa-scale systems and would additional make each component increasingly unreliable; see Lammers (2010); Winstead and Rodrigues (2012); Cappello (2009) and references therein. Therefore, to guarantee a reliable system, high energy costs are necessary, which creates another grand challenge for exa-scale computing.…”

Section: Introductionmentioning

confidence: 99%

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Adaptive control in roll-forward recovery for extreme scale multigrid

Huber

Rüde

Wohlmuth

2018

The International Journal of High Performance Computing Applica

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With the increasing number of compute components, failures in future exa-scale computer systems are expected to become more frequent. This motivates the study of novel resilience techniques. Here, we extend a recently proposed algorithm-based recovery method for multigrid iterations by introducing an adaptive control. After a fault, the healthy part of the system continues the iterative solution process, while the solution in the faulty domain is re-constructed by an asynchronous on-line recovery. The computations in both the faulty and healthy subdomains must be coordinated in a sensitive way, in particular, both under and over-solving must be avoided. Both of these waste computational resources and will therefore increase the overall time-to-solution. To control the local recovery and guarantee an optimal re-coupling, we introduce a stopping criterion based on a mathematical error estimator. It involves hierarchical weighted sums of residuals within the context of uniformly refined meshes and is well-suited in the context of parallel high-performance computing. The re-coupling process is steered by local contributions of the error estimator. We propose and compare two criteria which differ in their weights. Failure scenarios when solving up to 6.9 · 10 11 unknowns on more than 245 766 parallel processes will be reported on a state-of-the-art peta-scale supercomputer demonstrating the robustness of the method.

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Section: Introductionmentioning

confidence: 99%

“…Removing such power-hungry hardware may be necessary to operate exa-scale systems due to its high energy costs. On the other hand, it would additionally make each component increasingly unreliable (see Cappello, 2009; Lammers, 2010; Winstead and Rodrigues, 2012, and references therein).…”

Section: Introductionmentioning

confidence: 99%

Adaptive control in roll-forward recovery for extreme scale multigrid

Huber

Rüde

Wohlmuth

2018

The International Journal of High Performance Computing Applica

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“…In [3] the scaling trend of the energy efficiency of analog and digital decoders has been investigated based on published works over the last decade. There, also an efficient digital LDPC decoder is presented for sub-threshold (sub-) operation, which is evaluated via simulations based on the models described in [4] and [5].…”

Section: Introductionmentioning

confidence: 99%

Low Power Analog and Digital (7,5) Convolutional Decoders in 65 nm CMOS

Meraji

Sherazi

Anderson

et al. 2015

IEEE Trans. Circuits Syst. I

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Targeting emerging energy constrained bio-implantable or wearable wireless devices, this work presents design space exploration of decoding circuits for convolutional codes in 65 nm CMOS for ultra-low power operation. Decoders operating in digital and analog domains are designed and measured for energy efficiency, bit error rate (BER) performance and throughput. For the analog decoders which are sensitive to noise and device mismatch, the overall effects of transistor dimensions on the output BER are also investigated. The digital implementation with 0.11 area consumes minimum energy at 0.32 V supply, which gives 9 pJ/b energy efficiency at 125 kb/s and 2.9 dB coding gain. Likewise, in analog domain, three decoding circuits are fabricated that share the same topology and design, except for transistor dimensions. The largest analog decoding core (AD1) takes 0.104 and the other two (AD2 and AD3) are 0.035 and 0.015 , respectively. Consequently, coding gain in trade-off with silicon area and throughput is presented. The analog decoders operate with 0.8 V supply, and 2.3 dB coding gain with 10 pico-Joules per bit (pJ/b) energy efficiency is achieved at 2 Mbps.Index Terms-Circuits and systems for coding in communication systems, circuits for wearable/implantable (bio) electronics, design space exploration, low power design.

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Performance of a high-speed transcutaneous link with error correction coding

Toribio

Winstead

2013

2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

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A Register Transfer Level (RTL) design that integrates a figure-8 multi-band inductive link (MIL), a bi-level pulse harmonic modulation (PHM) system, and a Gallager A decoder is presented and verified. Integrating this MIL with a PHM system can lead to optimizing power efficiency, data rate, and transmitter power consumption in near field transcutaneous wireless communication systems for cortical implants (CI). Also, a technique to increase the data rate of PHM systems based in multi-level transmission (MLT) is presented. MLT is an attractive solution to increasing data rates in PHM systems while meeting power consumption constraints, since it does not require increasing the frequency of the harmonics generated in the PHM receiver. Verilog Analog Mixed Signal (AMS) was used to verify these systems. The distance between external and implanted coils was modeled to be 10 mm.From the power interference characterization of the bi-level system, it was observed that for every value of the coupling coefficient between the power transmitter coil and data receiver coil (k 14 ), there is a different comparator reference voltage that can minimize the bit error rate (BER) of the system and optimize decoder performance. Moreover, it is shown that as k 14 increases, this optimal reference voltage also increases. Therefore, it is expected that a control system that could adapt the comparator reference voltages to changes in (k 14 ), could enhance robustness of PHM systems against factors that can increase MIL power iv interference, such as misalignments. From the verification of the MLT technique, it was observed that the optimal delay between initiation and suppression pulses (t d ) of a PHM system varies with respect to initiation pulse amplitudes, contrary to what had been stated in the past in previous PHM system verifications. Furthermore, it is concluded that, unless the pulse pattern generator (PPG) is designed to vary t d according to the initiation pulse transmitted, MLT-based PHM systems would be too vulnerable to non-idealities, such as noise and misalignments, preventing its feasibility. From the transmitter (TX) clock jitter characterizations, it was concluded that as the PHM levels of transmission increase, systems become more sensitive to jitters. Finally, the Gallager A decoder was found powerful in enhancing the robustness of PHM systems against power interference, TX clock jitter, and noise. Cortical implants (CI) can be used in medicine to treat neurological disorders, and to serve as substitutes of damaged organs in the nervous system. Currently, active research is being developed in the wireless data and power transfer to CIs, in order to avoid frequent surgical interventions to replace batteries and potential paths of infection due to wires breaching the skin. In this paper, we consider performance optimization strategies for a pulse-based wireless link that have been proposed recently. We consider two enhancements that may allow for increased throughput in this system. First, a low-power error-correcting ...

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Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub-$V_{ \rm T}$ Operation

Cited by 6 publications

References 27 publications

Adaptive control in roll-forward recovery for extreme scale multigrid

Adaptive control in roll-forward recovery for extreme scale multigrid

Low Power Analog and Digital (7,5) Convolutional Decoders in 65 nm CMOS

Performance of a high-speed transcutaneous link with error correction coding

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