Ultra-low-power carbon nanotube FET-based quaternary logic gates

Sharifi, Fazel; Moaiyeri, Mohammad Hossein; Navi, Keivan; Bagherzadeh, Nader

doi:10.1080/21681724.2016.1138506

Cited by 11 publications

(12 citation statements)

References 20 publications

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“…The effectiveness of temperature variations on SRAM stability in terms of V DR process in the presence of other TT, SS, SF, FS, FF corner conditions using the proposed algorithm in Fig. 11 As the obtained results reveal, it can be concluded that V DR increases with temperature for TT, FF, slow-fast (SF) (0.4 Volt /0°C) and fast-slow (FS) (0.65 Volt / 80 °C) in all structures based on Si-MOSFET technology node, while decreases for the FS and SS corners, where due to the high thermal conductivity (stability) of carbon atoms in CNT-MOSFETs [38], the V DR metric for the suggested bit-cell and 6T CNT-MOSFET are less sensitive to the temperature variation process than other state-of-the art counterpart bit-cells. Finally, the distance of the worst result for VDR in the presence of temperature changes in the TT corner based on the algorithm and MC from the simulation for cell [32] in Fig.…”

Section: Evaluation Of Comprehensive Parameters For Vdr-based Bit Cellsmentioning

confidence: 75%

A wrap-gate CNT-MOSFET based SRAM bit-cell with asymmetrical ground gating and built-in read-assist schemes for limited-energy environments application

Darabi

Salehi

Abiri

2021

Preprint

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Today, designing low-power single-bit SRAM structures with the ability to operate regularly at low supply voltages and with high immunity against standard radiation particles impact is challenging for designers. In the present article, a novel design of a low-power radiation-hardened single-ended SRAM bit-cell (UPRHSE) based on gate-diffusion input (GDI) method using gate-all-around carbon nano-tube (CNT) MOSFETs (GAA CNT-MOSFETs) along with dual-chirality/multiple-diameter technique for CNTs with an asymmetric virtual ground gating and built-in read-assist schemes with inherent single-node event upset (SEU) preventive and self-correction capabilities and a high degree of robustness against multiple-node event upsets (MEUs) in the presence of more consumption area storage has been proposed. In order to investigate single/double upset injection circuit model using the structure of the T-connected pseudo resistors (TPRs) has been proposed. Also, based on the analytical-compact model, an equation for calculating the data-retention voltage (VDR) metric for the suggested bit-cell structure and an algorithm for facile estimate of VDR for other bit-cell architectures is presented. The results of extensive Monte-Carlo (MC) simulations to evaluate the proposed bit-cell indicate larger noise margins, acceptable yield, less sensitivity to process, voltage and temperature (PVT) variations, higher critical charge and consequence more robustness to soft errors with high reliability of data storage in standby mode in the presence of voltage conditions lower than the nominal power supply, and better results in other comprehensive figure of merits (FoMs) criteria compared to nanotechnology-based state-of-the-art radiation-hardened (rad-hard) bit-cell circuits with the same number of transistors in the 16 nm technology node. So, the proposed UPRHSE design can be a reasonable choice for applications that demands high stability, impact resistance to radiation particles and extremely low power in a radiation abundant environment with limited-energy sources. Finally, in order to use the suggested UPRHSE bit-cell in a real application with secure data transfer approach, the suggested structure is employed for storing. The results show the better performance of UPRHSE in terms of other comprehensive FoMs based on PSNR and MSSIM metric to evaluate the appropriate accuracy in pixel-by-pixel image compared to other well-known counterpart designs.

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Section: Evaluation Of Comprehensive Parameters For Vdr-based Bit Cellsmentioning

confidence: 75%

A wrap-gate CNT-MOSFET based SRAM bit-cell with asymmetrical ground gating and built-in read-assist schemes for limited-energy environments application

Darabi

Salehi

Abiri

2021

Preprint

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“…In the above multiplier circuit, 53 CNTFET transistors were used to create the product and carry operators, and one power supply was used for the MUX units and control circuits. whereas the space applied decreased by 43.62% compared to [13] and by 61.59% compared to the first design [16]. The operators also decreased the power consumption by 98.46% compared to [13] and 98.26% compared to [16].…”

Section: Proposed Circuitsmentioning

confidence: 99%

“…whereas the space applied decreased by 43.62% compared to [13] and by 61.59% compared to the first design [16]. The operators also decreased the power consumption by 98.46% compared to [13] and 98.26% compared to [16].…”

Section: Proposed Circuitsmentioning

confidence: 99%

Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors

2021

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In this study, new multiplier and adder method designs with multiplexers are proposed. The designs are based on quaternary logic and a carbon nanotube field‐effect transistor (CNTFET). The design utilizes 4 × 4 multiplier blocks. Applying specific rotational functions and unary operators to the quaternary logic reduced the power delay produced (PDP) circuit by 54% and 17.5% in the CNTFETs used in the adder block and by 98.4% and 43.62% in the transistors in the multiplier block, respectively. The proposed 4 × 4 multiplier also reduced the occupied area by 66.05% and increased the speed circuit by 55.59%. The proposed designs are simulated using HSPICE software and 32 nm technology in the Stanford Compact SPICE model for CNTFETs. The simulated results display a significant improvement in the fabrication, average power consumption, speed, and PDP compared to the current best‐performing techniques in the literature. The proposed operators and circuits are evaluated under various operating conditions, and the results demonstrate the stability of the proposed circuits.

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“…The primary difference between the CNTFETs and MOSFETs is in its carrier mobility and driving current strengths, which are the same only for CNTFETs of both P and N models but not for MOSFETs. The flexibility is afforded to CNTFETs of more compact designs where the scaling and sizing adjustments are carried out easily in highly complex circuits [17]. The more analogous behaviour in I-V characteristics of the CNTFET in contrast to MOSFET is a crucial enhancement in CNTFET.…”

Section: The Behavioural Model Of the Cntfetsmentioning

confidence: 99%

“…This causes nonmobility charge carriers due to the 1D ballistic transport. It is established as an emerging and reliable device in view its aforesaid properties substituting conventional silicon technology [17,22].…”

Section: Heavily Doped Cnt Segments For Source/drainmentioning

confidence: 99%

An Operational Transconductance Amplifiers Based Sinusoidal Oscillator Using CNTFETs

Bhargav

Srinivasulu

Pal

2018

2018 International Conference on Applied Electronics (AE)

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1 Abstract-A new sinusoidal oscillator using Carbon Nanotube Field Effect Transistors (CNTFET) based Operational Transconductance Amplifiers (CNOTA) with grounded capacitors is presented in this paper. The proposed current-mode oscillator thus implemented and having grounded capacitor feature, fulfils the need for realizations of systems used in combination with various other systems/ subsystems -both voltage-mode and current mode. It also ensures simplicity in implementation by using a single-ended CNOTA. The analytical model is given for the circuit leading to fulfilment of the condition of oscillation at tuned frequency. The proposed sinusoidal oscillator is primarily used in the field of signal dispensation applications, telecommunication networks, communication-equipment and control modules. The benefits derived from the introduced model are validated by simulation carried out at a supply voltage of ±1.8 V in Cadence virtuoso using spectre model libraries. They are further tested with the aid of 32 nm model of Carbon Nanotube Field Effect Transistor (CNTFET) technology obtained through open source. The proposed design (and the model provided) is found to be in good agreement with the obtained results.

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Ultra-low-power carbon nanotube FET-based quaternary logic gates

Cited by 11 publications

References 20 publications

A wrap-gate CNT-MOSFET based SRAM bit-cell with asymmetrical ground gating and built-in read-assist schemes for limited-energy environments application

A wrap-gate CNT-MOSFET based SRAM bit-cell with asymmetrical ground gating and built-in read-assist schemes for limited-energy environments application

Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors

An Operational Transconductance Amplifiers Based Sinusoidal Oscillator Using CNTFETs

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