Ultra low-power bulk and gate-driven, class AB, sub-threshold transconductor

Abstract

Operational Transconductance Amplifier (OTA), is a main building block of analog signal systems. This paper presents a novel low-voltage and low-power rail-to-rail wide linear range OTA, operating in weak inversion region. The bulk and source-degenerated input stage provides, rail-to-rail input and output signal swings, whereas the class AB flipped voltage follower generates the bias current for the input stage. To enhance the current drive capability, a positive feedback has been employed at gates of input transistors. The OTA uses a single 0.5 V supply and dissipates 32 nW power to provide 38 dB gain and 50 kHz gain bandwidth product. The Cadence VIRTUOSO environment using UMC 0.18 m CMOS process technology has been used to simulate the proposed circuit. Simulation results showed that the circuit exhibits less than 52 dB total harmonic distortions, for 100 mV (p-p) signal at 200 Hz frequency in its unity gain configuration.

Sub-threshold, cascode compensated, bulk-driven OTAs with enhanced gain and phase-margin

“…The gate, source and bulk voltages modulate input pair drain currents under applied source-degeneration and gate-regeneration in the input core [22] producing effective transconductance G m given by ( )…”

“…The sub-threshold region operation need around 78 mV across the devices whereas strong inversion needs V OV 4200 mV, hence sub-threshold operation favors LV design [13]. So to design a high open loop gain and rail-to-rail linear OTA a source-degenerated, bulk-driven PMOS input core has been preferred in reported works [17][18][19][20][21][22]. The PMOS input core structure provides reduced flicker noise as compared to NMOS based design.…”

“…The first stage is comprised of an input core as in [17,22] followed by self-cascode current mirror load based CS amplifier. The second stage uses a simple MOS current source load in its CS configuration to ensure maximum output signal swing.…”

“…The input core (dashed area) consists of PMOS input pair (P 1 , P 2 ) with flipped voltage follower pair (P 3 , P 4 ) [17][18][19][20][21][22][23][24][25][26][27], source-degeneration resistor (2R S ) and diode connected load NMOS pair (N 1 , N 2 ). This input pair also includes a gate-regenerative feedback loop to enhance its transconductance [6,22]. The PMOS input core having bulk-driven differential pair is utilized to favor rail-to-rail input common mode range (ICMR), low-flicker noise and fabrication ability in standard n-tub CMOS technology in low-power supply environment.…”

“…The FVF MOS pair inserts a negative feedback loop and reduces the output impedance of input pair to support class AB operation, which increases its current drive capability to greater extent [17]. The bulk-driven input pair (P 1 , P 2 ) also utilizes the gate-regenerative loop to enhance its g mb [6,22]. In a two-stage OTA design balanced current mirror load reduces the device mismatch effect, whereas CS output stage provides better output swing than other configurations [28][29][30].…”