2016 IEEE Symposium on VLSI Technology 2016
DOI: 10.1109/vlsit.2016.7573384
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Ultra low p-type SiGe contact resistance FinFETs with Ti silicide liner using cryogenic contact implantation amorphization and Solid-Phase Epitaxial Regrowth (SPER)

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Cited by 20 publications
(14 citation statements)
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“…Third, the contact metal band alignment with the 2D semiconductor may be tuned by Fermi level depinning, 11 or alloying and strain, as was previously achieved by alloying Ge into Si source/drain regions to improve p-type contacts. 82 Further efforts in each of these areas are critical to reduce contact resistance below 100 Ω•μm for 2D semiconductors.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…Third, the contact metal band alignment with the 2D semiconductor may be tuned by Fermi level depinning, 11 or alloying and strain, as was previously achieved by alloying Ge into Si source/drain regions to improve p-type contacts. 82 Further efforts in each of these areas are critical to reduce contact resistance below 100 Ω•μm for 2D semiconductors.…”
Section: Resultsmentioning
confidence: 99%
“…Therefore, thicker 2D material at the contacts should be explored ( e.g ., by regrowth), not unlike “raised source/drain” of Si devices, where only the top one or two layers react with the metal and the bottom layers remain unharmed. Third, the contact metal band alignment with the 2D semiconductor may be tuned by Fermi level depinning, or alloying and strain, as was previously achieved by alloying Ge into Si source/drain regions to improve p -type contacts . Further efforts in each of these areas are critical to reduce contact resistance below 100 Ω·μm for 2D semiconductors.…”
Section: Resultsmentioning
confidence: 99%
“…1 In state-of-the-art 3D FinFET devices from the 22 nm node, Ti-based silicide, employed previously as the source/drain (S/D) contact material in 0.35-0.18 μm technology nodes, [2][3][4][5][6][7][8][9][10] has resurged in the manufacturing and research community. [11][12][13][14][15][16][17][18][19] For FinFET devices, the 3D architecture imposes unique constraints for the selection of S/D contact materials. It is well known that in the conventional planar device era, Ni(Pt)Si was widely employed as the S/D contact material because of its low thermal budget, low resistivity and low Si consumption.…”
mentioning
confidence: 99%
“…Metal silicides are extensively used in micro-electronics for contacting the source and drain regions of Si-based transistors [1]. C54-TiSi 2 was introduced in Complementary Metal Oxide Semiconductor (CMOS) devices for ultra-large scale integration during the early 90's and has subsequently been replaced by 5 sequentially CoSi 2 and NiSi for high-performance applications [2]. C54-TiSi 2 is still being used in traditional planar CMOS technology for applications with high reliability demands, e.g.…”
Section: Introductionmentioning
confidence: 99%
“…Preprint submitted to Journal of L A T E X Templates August 23, 2018 [15] Si(100) (101)//(111) (313)//(011) [17] (130)//(111) (004)//(110) [17,18] (101)//(111) (121)//(110) [17] applications. In recent years, Ti-based contacts have regained considerable attention for implementation in FinFET-technology through the formation of a thin Ti-Si compound, where Ti-based contacts offer a significant advantage over Ni because of the lower mobility of Ti in Si [3,4,5,6,7,8].…”
Section: Introductionmentioning
confidence: 99%