Ultra-Dense: an MCM-based 3-D digital signal processor

Segelken, J.M.; Wu, Lianmei; Lau, M.Y.; Tai, K.L.; Shively, R.R.; Grau, T.G.

doi:10.1109/33.159871

Cited by 20 publications

(3 citation statements)

References 3 publications

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“…A number of MCM-level/wafer-scale stacked substrate architectures have been put forth in the literature [19], [33], [44], [52], [54]. Proposed wire-based approaches for communicating between stacked substrates include thermomigrated aluminum feedthroughs [48], laser-drilled throughwafer vias [28], microspring bridges [33], chemically etched through-wafer vias [32], and collapsible pressure contacts such as "fuzz-buttons" [19].…”

Section: Related Workmentioning

confidence: 99%

“…Such 3D packaging solutions improve signaling speed by minimizing the length of chip-to-chip signal paths and improve throughput by maximizing the number of interconnects crossing the network bisection. 3D packaging technologies also enable ultra-compact MPPs [33], [44], [52] for embedded applications by minimizing system volume and footprint.…”

Section: Introductionmentioning

confidence: 99%

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The offset cube: a three-dimensional multicomputer network topology using through-wafer optics

Lacy

Cruz-Rivera

Wills

1998

IEEE Trans. Parallel Distrib. Syst.

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Three-dimensional packaging technologies are critical for enabling ultra-compact, massively parallel processors (MPPs) for embedded applications. Through-wafer optical interconnect has been proposed as a useful technology for building ultra-compact MPPs since it provides a simplified mechanism for interconnecting stacked multichip substrates. This paper presents the offset cube, a new network topology designed to exploit the packaging benefits of through-wafer optical interconnect in ultra-compact MPP systems. We validate the offset cube's topological efficiency by developing deadlock-free adaptive routing protocols with modest virtual channel requirements (only two virtual channels per link needed for full adaptivity). A preliminary analysis of router complexity suggests these protocols can be efficiently implemented in hardware. We also present a 3D mesh embedding for the offset cube. Network simulations show the offset cube performs comparably to a bidirectional 3D mesh of equal size under uniform, hot-spot, and trace-driven traffic loads. While the offset cube is not proposed as a general replacement for the mesh topology, it leverages the benefits of through-wafer optical interconnect more effectively than a mesh by completely eliminating chip-to-chip wires for data signals. Hence, the offset cube is an effective topology for interconnecting ultra-compact MCM-level MPP systems.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The offset cube: a three-dimensional multicomputer network topology using through-wafer optics

Lacy

Cruz-Rivera

Wills

1998

IEEE Trans. Parallel Distrib. Syst.

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“…Technology issues in implementing stacked structures have been addressed [l], [2] and novel 3-D structures realized. These include stacked silicon CMOS DRAM chips to realize compact Megabit memory modules [3], [4], information processing systems implemented on a stack of silicon integrated circuit wafers with vertical busses [5], [6], and 3-D modules used in the Cray-2 supercomputer system [7].…”

Section: Introduction He Principal Bottleneck In the Design And Dementioning

confidence: 99%

Performance, wireability, and cooling tradeoffs for planar and 3-D packaging architectures

George

Krusius

1995

IEEE Trans. Comp., Packag., Manufact. Technol. B

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Models for wiring length, cooling, wireability, and signal distribution are derived and integrated into a system-level performance metric used to compare packaging architectures for digital electronic systems. These include the common planar and stack-of-plane structures, in addition to fully 3-D structures with variable aspect ratios. This performance metric has been used to examine optimum packaging architectures for air and water-cooled systems as a function of a number of parameters including the total circuit count. The results show that none of these packaging architectures is always optimal. Rather, the optimum structure is determined by the specilic set of system conditions chosen. The reader may easily use this model in order to determine the "best" packaging architecture for system parameters not included in this paper.

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3-D Assemblies of Stacked Chips and other Thin Packages

Balde

2003

Emerging Technology in Advanced Packaging Series

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Ultra-Dense: an MCM-based 3-D digital signal processor

Cited by 20 publications

References 3 publications

The offset cube: a three-dimensional multicomputer network topology using through-wafer optics

The offset cube: a three-dimensional multicomputer network topology using through-wafer optics

Performance, wireability, and cooling tradeoffs for planar and 3-D packaging architectures

3-D Assemblies of Stacked Chips and other Thin Packages

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