Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

Su, Jian‐Wei; Si, Xin; Chou, Yen-Chi; Chang, Ting-Wei; Huang, Wei-Hsing; Tu, Yung-Ning; Liu, Ruhui; Lu, Pei-Jung; Liu, Chun‐Jen; Wang, Jinghong; Chung, Yen-Lin; Ren, Jin-Sheng; Chang, Fu-Chun; Wu, Yuan; Jiang, Hongwu; Huang, Shanshi; Li, Sih-Han; Sheu, Shyh-Shyuan; Wu, Chih-I; Lo, Chung-Chuan; Liu, Ren-Shuo; Hsieh, Chih-Cheng; Tang, Kea-Tiong; Yu, Shimeng; Chang, Meng‐Fan

doi:10.1109/jssc.2021.3108344

Cited by 31 publications

(10 citation statements)

References 43 publications

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“…As SRAM is a mature memory technology, there are a lot of fabricated SRAM-based IMC architectures shown in [41], [4], [42]. The SRAM implementation of both inference and training accelerator is illustrated in [43]. The fabricated RRAMbased IMC macros designs are shown in [48], [49].…”

Section: B Higher-bit Fixed-point Imc Computations For Qnnsmentioning

confidence: 99%

Towards Efficient In-Memory Computing Hardware for Quantized Neural Networks: State-of-the-Art, Open Challenges and Perspectives

Krestinskaya

Zhang

Salama

2023

IEEE Trans. Nanotechnology

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The amount of data processed in the cloud, the development of Internet-of-Things (IoT) applications, and growing data privacy concerns force the transition from cloud-based to edge-based processing. Limited energy and computational resources on edge push the transition from traditional von Neumann architectures to In-memory Computing (IMC), especially for machine learning and neural network applications. Network compression techniques are applied to implement a neural network on limited hardware resources. Quantization is one of the most efficient network compression techniques allowing to reduce the memory footprint, latency, and energy consumption. This paper provides a comprehensive review of IMC-based Quantized Neural Networks (QNN) and links software-based quantization approaches to IMC hardware implementation. Moreover, open challenges, QNN design requirements, recommendations, and perspectives along with an IMC-based QNN hardware roadmap are provided.

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Section: B Higher-bit Fixed-point Imc Computations For Qnnsmentioning

confidence: 99%

Towards Efficient In-Memory Computing Hardware for Quantized Neural Networks: State-of-the-Art, Open Challenges and Perspectives

Krestinskaya

Zhang

Salama

2023

IEEE Trans. Nanotechnology

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“…In recent compute-in-memory design, convolution neural networks became the mainstream [3], [8], [12], [13], [59]. Table VI summarizes the test accuracy from the recent compute-in-memory demonstrations [3], [7], [8], [10], [43], [59], [62]- [64]. For the MNIST dataset, the range of test accuracy is 97%∼99.63%, depending on the design and the ML algorithm.…”

Section: B Test Accuracymentioning

confidence: 99%

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning

Kim

Xie

Chen

et al. 2022

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Artificial intelligence (AI) and machine learning (ML) are revolutionizing many fields of study, such as visual recognition, natural language processing, autonomous vehicles, and prediction. Traditional von-Neumann computing architecture with separated processing elements and memory devices have been improving their computing performances rapidly with the scaling of process technology. However, in the era of AI and ML, data transfer between memory devices and processing elements becomes the bottleneck of the system. To address this data movement issue, memory-centric computing takes an approach of merging the memory devices with processing elements so that computations can be done in the same location without moving any data. Processing-In-Memory (PIM) has attracted research community's attention because it can improve the energy efficiency of memory-centric computing systems substantially by minimizing the data movement. Even though the benefits of PIM are well accepted, its limitations and challenges have not been investigated thoroughly. This paper presents a comprehensive investigation of state-of-the-art PIM research works based on various memory device types, such as static-random-access-memory (SRAM), dynamic-random-access-memory (DRAM), and resistive memory (ReRAM). We will present the overview of PIM designs in each memory type, covering from bit cells, circuits, and architecture. Then, a new software stack standard and its challenges for incorporating PIM with the conventional computing architecture will be discussed. Finally, we will discuss various future research directions in PIM for further reducing the data conversion overhead, improving test accuracy, and minimizing intra-memory data movement.

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“…A peripheral circuit, which is same as LA [1], LA [3], and LA [4], while the rests have a type A peripheral circuit.…”

Section: Cwl[15:0] Multplication Dac a A A A A A A B La[0]mentioning

confidence: 99%

A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing

Kim

Lee

Park

2022

Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

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This paper presents a low cost PMOS-based 8T (P-8T) SRAM Compute-In-Memory (CIM) architecture that efficiently performs the multiply-accumulate (MAC) operations between 4-bit input activations and 8-bit weights. First, bit-line (BL) chargesharing technique is employed to design the low-cost and reliable digital-to-analog conversion of 4-bit input activations in the proposed SRAM CIM, where the charge domain analog computing provides variation tolerant and linear MAC outputs. The 16 local arrays are also effectively exploited to implement the analog multiplication unit (AMU) that simultaneously produces 16 multiplication results between 4-bit input activations and 1-bit weights. For the hardware cost reduction of analog-to-digital converter (ADC) without sacrificing DNN accuracy, hardware aware system simulations are performed to decide the ADC bitresolutions and the number of activated rows in the proposed CIM macro. In addition, for the ADC operation, the AMU-based reference columns are utilized for generating ADC reference voltages, with which low-cost 4-bit coarse-fine flash ADC has been designed. The 256×80 P-8T SRAM CIM macro implementation using 28nm CMOS process shows that the proposed CIM shows the accuracies of 91.46% and 66.67% with CIFAR-10 and CIFAR-100 dataset, respectively, with the energy efficiency of 50.07-TOPS/W.

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Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

Cited by 31 publications

References 43 publications

Towards Efficient In-Memory Computing Hardware for Quantized Neural Networks: State-of-the-Art, Open Challenges and Perspectives

Towards Efficient In-Memory Computing Hardware for Quantized Neural Networks: State-of-the-Art, Open Challenges and Perspectives

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning

A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing

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