“…Interface traps can also capture holes, leading to a lower current and a lower implied mobility. The interface trap density ( D it ) at the semiconductor–dielectric interface can be estimated from the sub-threshold slope (SS) using eqn (3): 5,34
The extracted trap density is 2.6 × 10 12 , 6.7 × 10 12 , 2.4 × 10 13 , and 6.0 × 10 13 cm −2 eV −1 for Device 1, Device 2, Device 3, and Device 4, respectively. Overall, SiO 2 with the lowest defect state, the lowest surface energy, and the largest grain size has the lowest interface scattering.…”