Two-stage low power test data compression for digital VLSI circuits

Thilagavathi, K.; Sivanantham, S.

doi:10.1016/j.compeleceng.2018.07.009

Cited by 13 publications

(5 citation statements)

References 21 publications

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“…Volume of data sequences are reduced along with its memory requirement. In paper [33], a novel and hybrid X-filling and compression technique which has two stages of compressions for digital circuits is proposed which greatly reduces the power consumption and data volume. Modified 4m filling is combined with adjacent filling techniques to reduce the switching activities.…”

Section: Related Workmentioning

confidence: 99%

Efficient Test Data Compression for SoC through ASRL with Improved Dictionary based Compression Technique

Anandhi¹,

Neela²,

Rani³

2019

IJITEE

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Data compression techniques are explored in this paper, through which system memory size gets reduced in an effective manner. The size of the memory is always a key constraint in the embedded system. Larger memory size increases the bandwidth utilization which raises the cost of hardware and data transmission. It is difficult to transfer large data through the network. Data compression encoding technique is utilized to minimize the data size. The redundant character is reduced or encoding the bits in data is done to reduce the data size. The proposed system focused on lossless compression where the original information of the data is available even though the data size is compressed. The data compression is done through a dictionary-based compression algorithm and Alternating Statistical Run Length code (ASRL). In the existing system of ASRL, the compression ratio is about 65.16% and 67.18% for two benchmark circuits S5378 &S9234. The compression ratio of the test data is increased by combining the ASRL and Improved Dictionary-Based compression Technique. The proposed combined technique provides 80.25%& 82.5% compression ratio for two benchmark circuits S5378 &S9234. This reduces the power dissipation problem in the circuit and thereby the area of the circuit gets reduced.

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Section: Related Workmentioning

confidence: 99%

Efficient Test Data Compression for SoC through ASRL with Improved Dictionary based Compression Technique

Anandhi¹,

Neela²,

Rani³

2019

IJITEE

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“…Though, the computational cost has been considerably reduced as compared to DCT, but the compression performance was roughly like DCT performance. Further, the Daubechies wavelet filters are utilized for image compression, which is applied to DWT to extract the various properties of time and frequency [20]. Usually, the architectures of set partitioning in hierarchical trees (SPHIT) were employed for image/video compression systems, that need higher memory and huge computational time with complicated sorting algorithms.…”

Section: Introductionmentioning

confidence: 99%

Quantum-dot Cellular Automata Based Lossless CFA Image Compression Using Improved and Extended Golomb-rice Entropy Coder

2022

IJIES

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This article presents an efficient hardware architecture of lossless image compression mechanism using colour filter array (CFA) for wireless camera networks. Recently, Quantum-dot cellular automata (QCA) technology has been widely using in the field of VLSI, thus the proposed compressor is developed using QCA technology to mitigate the area, and power as compared to standard CMOS technology. In addition, an improved and extended Golomb-Rice entropy coder (IEGREC) is proposed to reduce the memory requirement, and computational complexity. The IEGREC approach eliminates the requirement of context module, which is a major component in lossless image compressor architectures and its memory to lessen the hardware resource utilization. Further, to maintain the pixel connectivity and higher compression ratio (CR), the proposed architecture utilizes the adaptive Golomb-Rice (GR) parameter prediction and control module. Finally, packer module is used to maintain the flow of output compressed bit stream. The extensive simulation results show that proposed QCA-IEGREC method performs superior as compared to state-of-art approaches in terms of lesser area as 3700 gate count, and reduced power of 1.02 mW, and even image quality statistics such as 18.78dB of peak signal-to-noise ratio (PSNR), 152.3 of figure-ofmerit (FOM), and 29.3 of CR.

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“…Thilagavathi et al [19] have presented a new test power and volume reduction technique by integrating hybrid X-fill and two-stage test data compression (TS-TDC) schemes to use in digital VLSI circuits. The hybrid X-filling integrates adjacent filling as well as modified 4 m filling method to decrease the scan cells switching activities.…”

Section: Introductionmentioning

confidence: 99%

On Reducing Test Data Volume for Circular Scan Architecture Using Modified Shuffled Shepherd Optimization

et al. 2021

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In this manuscript, a novel test data compression (TDC) system is proposes for reducing a test data volume (TDV) for circular scan (CS) architecture. A modified version of meta-heuristic population based optimization approach, hence it is called shuffled shepherd optimization (SSO) and it is used to optimize the conflicting bit minimization (CBM) problem. In CS framework, TDC is reached by upgrading only the conflicting bits among template pattern, real test pattern. Reduced test data volume and test application time are achieved by diminishing the Hamming distance between the currently captured response and the subsequent test vector. The CBM issue is formulated by a traveling salesman problem (TSP). Here, the test vectors are assumed by cities, the HD among test vectors a pair is assumed by distance of interurban. A modified version of the SSO algorithm called as MSSO is applied in combination using mutation operator for solving the issue of CBM. Experimental outcomes display the proposed TDC method using MSSO achieves an average development of 8.36% in compression ratio (CR) as well as 6.77% in TAT is attained by reducing a TDV. This proposed approach outperforms other state-of-art test data compression schemes by providing improved CR, TAT reduction and TDV reduction.

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Two-stage low power test data compression for digital VLSI circuits

Cited by 13 publications

References 21 publications

Efficient Test Data Compression for SoC through ASRL with Improved Dictionary based Compression Technique

Efficient Test Data Compression for SoC through ASRL with Improved Dictionary based Compression Technique

Quantum-dot Cellular Automata Based Lossless CFA Image Compression Using Improved and Extended Golomb-rice Entropy Coder

On Reducing Test Data Volume for Circular Scan Architecture Using Modified Shuffled Shepherd Optimization

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