Two soft-error mitigation techniques for functional units of DSP processors

Abstract

This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic has been elaborated with a fast recovery mechanism to isolate the fault-free functional units and re-execute the erroneous instruction. These techniques have been implemented on a DSP processor in order to assess the achieved fault-tolerance versus the imposed overheads.

Modelling and mitigation of soft-errors in CMOS processors

“…This method benefits from the architecture of DSP processors to halt the correct functional units for one clock cycle while re-execute the unit that was hit by a soft-error. Experiments show that the proposed method can mitigate half of the occurred soft-errors while the imposed overhead in terms of silicon area is only 10% and the speed of the processor is similar to the baseline design [Roh13c,Roh14a].…”