Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports

Lin, Zhiting; Zhu, Zhouyuan; Zhan, Honglan; Peng, Chunyu; Wu, Xiulong; Yuan, Yao; Niu, Jianchao; Chen, Junning

doi:10.1109/jssc.2021.3061260

Cited by 39 publications

(12 citation statements)

References 26 publications

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“…where I CL,i = I a when W[i] and IN[i] are high, otherwise I CL,i = 0. The computing port CL and the read-write port BL are decoupled, which can improve the computation stability and the amount of data that can be simultaneously accessed [38].…”

Section: B the Dual-mode Bit-cellmentioning

confidence: 99%

Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell

Cai¹,

Guo²,

Liu³

et al. 2021

Preprint

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In-memory computing (IMC) is an effectual solution for energy-efficient artificial intelligence applications. Analog IMC amortizes the power consumption of multiple sensing amplifiers with analog-to-digital converter (ADC), and simultaneously completes the calculation of multi-line data with high parallelism degree. Based on a universal one-transistor one-magnetic tunnel junction (MTJ) spin transfer torque magnetic RAM (STT-MRAM) cell, this paper demonstrates a novel tunneling magnetoresistance (TMR) ratio magnifying method to realize analog IMC. Previous concerns include low TMR ratio and analog calculation nonlinearity are addressed using device-circuit interaction. Peripheral circuits are minimally modified to enable in-memory matrix-vector multiplication. A current mirror with feedback structure is implemented to enhance analog computing linearity and calculation accuracy. The proposed design maximumly supports 1024 2-bit input and 1-bit weight multiply-andaccumulate (MAC) computations simultaneously. The 2-bit input is represented by the width of the input (IN) pulses, while the 1-bit weight is stored in STT-MRAM and the ×7500 magnified TMR (m-TMR) ratio is obtained by latching. The proposal is simulated using 28-nm CMOS process and MTJ compact model. The integral nonlinearity is reduced by 57.6% compared with the conventional structure. 9.47-25.4 TOPS/W is realized with 2-bit input, 1-bit weight and 4-bit output convolution neural network (CNN).

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Section: B the Dual-mode Bit-cellmentioning

confidence: 99%

Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell

Cai¹,

Guo²,

Liu³

et al. 2021

Preprint

View full text Add to dashboard Cite

show abstract

“…1−4 However, with the development of artificial intelligence (AI) processors, modern computing systems require intensive computations and a large memory capacity. 5,6 AI processors typically use convolutional neural networks (CNN) comprising several convolution and fully connected (FC) layers. In particular, the convolution and FC layers require parallel multiply-and-accumulation (MAC) operations, requiring intensive data movement.…”

Section: Introductionmentioning

confidence: 99%

“…7−9 However, in the von Neumann architecture, a large latency and energy consumption exist owing to the frequent data movement between the central processing unit and memory. [5][6][7]10 In this regard, processing-in-memory (PIM) has been introduced as a promising approach. 5−9,11−17 Inspired by the neural network of the human brain, the PIM architecture reduces the latency and energy consumption in data movement by allowing highly parallel computing in the memory module (Figure 1a).…”

Section: Introductionmentioning

confidence: 99%

“…Over the past 5 decades, computing science and technology based on the von Neumann architecture have provided outstanding advances in every field. − However, with the development of artificial intelligence (AI) processors, modern computing systems require intensive computations and a large memory capacity. , AI processors typically use convolutional neural networks (CNN) comprising several convolution and fully connected (FC) layers. In particular, the convolution and FC layers require parallel multiply-and-accumulation (MAC) operations, requiring intensive data movement. − However, in the von Neumann architecture, a large latency and energy consumption exist owing to the frequent data movement between the central processing unit and memory. − , In this regard, processing-in-memory (PIM) has been introduced as a promising approach. − ,− Inspired by the neural network of the human brain, the PIM architecture reduces the latency and energy consumption in data movement by allowing highly parallel computing in the memory module (Figure a).…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors

Kim

et al. 2022

ACS Appl. Mater. Interfaces

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Ferroelectric field-effect transistors (FeFETs) have attracted enormous attention for low-power and high-density nonvolatile memory devices in processing-inmemory (PIM). However, their small memory window (MW) and limited endurance severely degrade the area efficiency and reliability of PIM devices. Herein, we overcome such challenges using key approaches covering from the material to the device and array architecture. High ferroelectricity was successfully demonstrated considering the thermodynamics and kinetics, even in a relatively thick (≥30 nm) ferroelectric material that was unexplored so far. Moreover, we employed a metal−ferroelectric−metal− insulator−semiconductor architecture that enabled desirable voltage division between the ferroelectric and the metal−oxide−semiconductor FET, leading to a large MW (∼11 V), fast operation speed (<20 ns), and high endurance (∼10 11 cycles) characteristics. Subsequently, reliable and energy-efficient multiply-and-accumulation (MAC) operations were verified using a fabricated FeFET-PIM array. Furthermore, a system-level simulation demonstrated the high energy efficiency of the FeFET-PIM array, which was attributed to charge-domain computing. Finally, the proposed signed weight MAC computation achieved high accuracy on the CIFAR-10 dataset using the VGG-8 network.

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“…The concept of content addressable memory (CAM) has gained widespread interest owing to its data storage ability and the capability of searching data in parallel and can thus be considered a special IMC [5][6][7]. CAM can be divided into binary CAM (BCAM), which requires precise matching, and ternary CAM (TCAM), which requires approximate matching [8].…”

mentioning

confidence: 99%

Static random‐access memory with embedded arithmetic logic units for in‐memory computing and ternary content addressable memory operation

Lin

Fan

et al. 2022

Electronics Letters

Self Cite

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In‐memory computing (IMC) is a novel computing architecture that presents considerable potential in solving the data transmission and energy consumption problems faced by the von Neumann architecture. The compound Boolean logic operation (CBLO) is a crucial component of most advanced computing platforms. This study presents a static random‐access memory array structure comprising configurable embedded arithmetic logic units (ALUs), which can realize four types of CBLOs within a single cycle. The proposed structure can also form the ternary content addressable memory (TCAM) for ternary searching by configuring signal lines and sense amplifiers. The authors performed 5000 trials of the Monte Carlo simulation for four types of CBLOs. The results of all four types were observed to be accurate, and the delay of the TCAM was observed to be as low as 141 ps, which improves the parallelism of IMC, reduces power consumption, and significantly reduces calculation delay.

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Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports

Cited by 39 publications

References 26 publications

Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell

Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell

Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors

Static random‐access memory with embedded arithmetic logic units for in‐memory computing and ternary content addressable memory operation

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